IC41C4100IC41LV4100
Document Title1Mx4 bit Dynamic RAM with EDO Page Mode
Revision HistoryRevision No0A
HistoryInitial Draft
Draft DateSeptember 5,2001
RemarkThe attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications andproducts. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
1
元器件交易网www.cecb2b.com
IC41C4100IC41LV4100
1M x 4 (4-MBIT) DYNAMIC RAMWITH EDO PAGE MODE
FEATURES
Extended Data-Out (EDO) Page Mode access cycleTTL compatible inputs and outputs; tristate I/ORefresh Interval: 1024 cycles /16 ms
Refresh Mode: RAS-Only, CAS-before-RAS (CBR),Hidden
•Single power supply:
5V ± 10% (IC41C4100) 3.3V ± 10% (IC41LV4100)•Industrail Temperature Range -40oC to 85oC••••
DESCRIPTION
The ICSI IC41C4100 and IC41LV4100 is a 1,048,576 x 4-bit
high-performance CMOS Dynamic Random Access Memories.The IC41C4100 offer an accelerated cycle access called EDOPage Mode. EDO Page Mode allows 1024 random accesseswithin a single row with access cycle time as short as 12 ns per4-bit word.
These features make the IC41C4100and IC41LV4100 ideallysuited for, digital signal processing, high-performance audiosystems, and peripheral applications.
The IC41C4100 is packaged in a 20-pin 300mil SOJ and 300milTSOP-2.
KEY TIMING PARAMETERS
Parameter
Max. RAS Access Time (tRAC)Max. CAS Access Time (tCAC)
Max. Column Address Access Time (tAA)Min. EDO Page Mode Cycle Time (tPC)Min. Read/Write Cycle Time (tRC)
-353510181260
-505014252090
-6060153025110
Unitnsnsnsnsns
PIN CONFIGURATION20 (26) Pin SOJ, TSOP-2
I/O0I/O1WERASA9123452625242322GNDI/O3I/O2CASOEPIN DESCRIPTIONS
A0-A9I/O0-3WEOERASCASVcc
Address InputsData Inputs/OutputsWrite EnableOutput EnableRow Address StrobeColumn Address StrobePowerGroundNo Connection
A0A1A2A3VCC9101112131817161514A8A7A6A5A4GNDNC
2Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
元器件交易网www.cecb2b.com
IC41C4100IC41LV4100
FUNCTIONAL BLOCK DIAGRAMOEWECASCAS CLOCKGENERATORWE CONTROLLOGICSOE CONTROLLOGICCASWEOERASRAS CLOCKGENERATORDATA I/O BUSCOLUMN DECODERSSENSE AMPLIFIERSREFRESH COUNTERDATA I/O BUFFERSROW DECODERRASI/O0-I/O3MEMORY ARRAY1,048,576 x 4A0-A9ADDRESSBUFFERSIntegrated Circuit Solution Inc.
DR027-0A 09/05/2001
3
元器件交易网www.cecb2b.com
IC41C4100IC41LV4100
TRUTH TABLE
FunctionStandbyRead:Write: (Early Write)Read-WriteEDO Page-Mode ReadRASHLLLLLLLLLLL→H→LL→H→LLH→LCASHLLLH→LH→LL→HH→LH→LH→LH→LLLHLWEXHLH→LHHHLLH→LH→LHLXXOEAddress tR/tCXXLROW/COLXROW/COLL→HROW/COLLROW/COLLNA/COLLNA/NAXROW/COLXNA/COLL→HROW/COLL→HNA/COLLROW/COLXROW/COLXROW/NAXXI/OHigh-ZDOUTDINDOUT, DINDOUTDOUTDOUTDINDINDOUT, DINDOUT, DINDOUTDINHigh-ZHigh-ZEDO Page-Mode WriteEDO Page-ModeRead-WriteHidden RefreshRAS-Only RefreshCBR Refresh1st Cycle:2nd Cycle:Any Cycle:1st Cycle:2nd Cycle:1st Cycle:2nd Cycle:ReadWrite4Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
元器件交易网www.cecb2b.com
IC41C4100IC41LV4100
Functional Description
The IC41C4100 and IC41LV4100 is a CMOS DRAMoptimized for high-speed bandwidth, low power applica-tions. During READ or WRITE cycles, each bit is uniquelyaddressed through the 20 address bits. These are entered10 bits (A0-A9) at a time. The row address is latched by theRow Address Strobe (RAS). The column address is latchedby the Column Address Strobe (CAS) .
Refresh Cycle
To retain data, 1024 refresh cycles are required in each16 ms period. There are two ways to refresh the memory.1.By clocking each of the 1024 row addresses (A0 throughA9) with RAS at least once every 16 ms. Any read, write,read-modify-write or RAS-only cycle refreshes the ad-dressed row.
2.Using a CAS-before-RAS refresh cycle. CAS-before-RAS refresh is activated by the falling edge of RAS,while holding CAS LOW. In CAS-before-RAS refreshcycle, an internal 10-bit counter provides the row ad-dresses and the external address inputs are ignored.CAS-before-RAS is a refresh-only mode and no dataaccess or device selection is allowed. Thus, the outputremains in the High-Z state during the cycle.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it isterminated by returning both RAS and CAS HIGH. Toensures proper device operation and data integrity anymemory cycle, once initiated, must not be ended oraborted before the minimum tRAS time has expired. A newcycle must not be initiated until the minimum prechargetime tRP, tCP has elapsed.
Extended Data Out Page Mode
EDO page mode operation permits all 1024 columns withina selected row to be randomly accessed at a high data rate.In EDO page mode read cycle, the data-out is held to thenext CAS cycle’s falling edge, instead of the rising edge.For this reason, the valid data output time in EDO pagemode is extended compared with the fast page mode. Inthe fast page mode, the valid data output time becomesshorter as the CAS cycle time becomes shorter. Therefore,in EDO page mode, the timing margin in read cycle islarger than that of the fast page mode even if the CAS cycletime becomes shorter.
In EDO page mode, due to the extended data function, theCAS cycle time can be shorter than in the fast page modeif the timing margin is the same.
The EDO page mode allows both read and write opera-tions during one RAS cycle, but the performance isequivalent to that of the fast page mode in that case.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,whichever occurs last, while holding WE HIGH. Thecolumn address must be held for a minimum time specifiedby tAR. Data Out becomes valid only when tRAC, tAA, tCACand tOE are all satisfied. As a result, the access time isdependent on the timing relationships between theseparameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS andWE, whichever occurs last. The input data must be validat or before the falling edge of CAS or WE, whicheveroccurs first.
Power-On
After application of the VCC supply, an initial pause of200 µs is required followed by a minimum of eight initial-ization cycles (any combination of cycles containing aRAS signal).
During power-on, it is recommended that RAS track withVCC or be held at a valid VIH to avoid current surges.
Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
5
元器件交易网www.cecb2b.com
IC41C4100IC41LV4100
ABSOLUTE MAXIMUM RATINGS(1)
SymbolVTVCCIOUTPDTATSTG
Parameters
Voltage on Any Pin Relative to GNDSupply Voltage
Output CurrentPower Dissipation
Commercial Operation TemperatureIndustrial Operationg TemperatureStorage Temperature
5V3.3V5V3.3V
Rating–1.0 to +7.0–0.5 to +4.6–1.0 to +7.0–0.5 to +4.6
5010 to +70–40 to +85–55 to +125
UnitVVmAW°C°C°C
Note:
1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanentdamage to the device. This is a stress rating only and functional operation of the device at theseor any other conditions above those indicated in the operational sections of this specification isnot implied. Exposure to absolute maximum rating conditions for extended periods may affectreliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
SymbolVCCVIHVILTA
ParameterSupply VoltageInput High VoltageInput Low Voltage
Commercial Ambient TemperatureIndustrial Ambient Temperature
5V3.3V5V3.3V5V3.3V
Min.4.53.02.42.0–1.0–0.30–40
Typ.5.03.3——————
Max.5.53.6VCC + 1.0VCC + 0.30.80.87085
UnitVVV°C°C
CAPACITANCE(1,2)
SymbolCIN1CIN2CIO
Parameter
Input Capacitance: A0-A9
Input Capacitance: RAS, CAS, WE, OEData Input/Output Capacitance: I/O0-I/O3
Max.577
UnitpFpFpF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.2. Test conditions: TA = 25°C, f = 1 MHz.
6Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
元器件交易网www.cecb2b.com
IC41C4100IC41LV4100
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)SymbolParameterIILIIOVOHVOLICC1
Input Leakage CurrentOutput Leakage CurrentOutput High Voltage LevelOutput Low Voltage LevelStandby Current: TTL
Test Condition
Any input 0V ≤ VIN ≤ Vcc
Other inputs not under test = 0VOutput is disabled (Hi-Z)0V ≤ VOUT ≤ VccIOH = –2.5 mAIOL =+2.1mARAS, CAS ≥ VIH
Commerical5VIndustrial5VCommerical3.3VIndustrial3.3V
5V
3.3V-35-50-60-35-50-60-35-50-60-35-50-60Speed
Min.–10–102.4———————————————————
Max.1010—0.4231210.5110958590807011095851109585
UnitµAµAVVmA
ICC2ICC3
Standby Current: CMOSOperating Current:
Random Read/Write(2,3,4)
Average Power Supply CurrentOperating Current:EDO Page Mode(2,3,4)
Average Power Supply CurrentRefresh Current:RAS-Only(2,3)
Average Power Supply CurrentRefresh Current:CBR(2,3,5)
Average Power Supply Current
RAS, CAS ≥ VCC – 0.2VRAS, CAS,
Address Cycling, tRC = tRC (min.)RAS = VIL, CAS,
Cycling tPC = tPC (min.)RAS Cycling, CAS ≥ VIHtRC = tRC (min.)RAS, CAS CyclingtRC = tRC (min.)
mAmA
ICC4mA
ICC5mA
ICC6mA
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper deviceoperation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.4. Column-address is changed once each EDO page cycle.5. Enables on-chip refresh and address counters.
Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
7
元器件交易网www.cecb2b.com
IC41C4100IC41LV4100
AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)SymboltRCtRACtCACtAAtRAStRPtCAStCPtCSHtRCDtASRtRAHtASCtCAHtARtRADtRALtRPCtRSHtCLZtCRPtODtOEtOEHCtOEPtOEStRCStRRHtRCHtWCHtWCRtWPtWPZtRWLtCWLtWCStDHR
Parameter
Random READ or WRITE Cycle TimeAccess Time from RAS(6, 7)Access Time from CAS(6, 8, 15)
Access Time from Column-Address(6)RAS Pulse WidthRAS Precharge TimeCAS Pulse Width(26)
CAS Precharge Time(9, 25)CAS Hold Time (21)
RAS to CAS Delay Time(10, 20)Row-Address Setup TimeRow-Address Hold Time
Column-Address Setup Time(20)Column-Address Hold Time(20)Column-Address Hold Time(referenced to RAS)
RAS to Column-Address Delay Time(11)Column-Address to RAS Lead TimeRAS to CAS Precharge TimeRAS Hold Time(27)
CAS to Output in Low-Z(15, 29)
CAS to RAS Precharge Time(21)Output Disable Time(19, 28, 29)Output Enable Time(15, 16)
OE HIGH Hold Time from CAS HIGHOE HIGH Pulse Width
OE LOW to CAS HIGH Setup TimeRead Command Setup Time(17, 20)Read Command Hold Time(referenced to RAS)(12)
Read Command Hold Time(referenced to CAS)(12, 17, 21)
Write Command Hold Time(17, 27)Write Command Hold Time(referenced to RAS)(17)
Write Command Pulse Width(17)
WE Pulse Widths to Disable OutputsWrite Command to RAS Lead Time(17)Write Command to CAS Lead Time(17, 21)Write Command Setup Time(14, 17, 20)
Data-in Hold Time (referenced to RAS)
-35Min.Max.60———352065351106063010180835301010500053051088030
—35101810K—10K——28—————20—————1210——————————————
-50Min.Max.90———503088501908084014250143530101050008408101414040
—50142510K—10K——36—————25—————1215——————————————
-60Min.Max.110———604010106020010010401530015353—10105000105010101515040
—60153010K—10K——45—————30—————1215——————————————
Unitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns
8Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
元器件交易网www.cecb2b.com
IC41C4100IC41LV4100
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)SymboltACHtOEHtDStDHtRWCtRWDtCWDtAWDtPCtRASPtCPAtPRWCtCOHtOFFtWHZtCLCHtCSRtCHRtORDtREFtT
Parameter
Column-Address Setup Time to CASPrecharge during WRITE CycleOE Hold Time from WE duringREAD-MODIFY-WRITE cycle(18)Data-In Setup Time(15, 22)Data-In Hold Time(15, 22)
READ-MODIFY-WRITE Cycle Time RAS to WE Delay Time duringREAD-MODIFY-WRITE Cycle(14)CAS to WE Delay Time(14, 20)
Column-Address to WE Delay Time(14)EDO Page Mode READ or WRITECycle Time(24)
RAS Pulse Width in EDO Page ModeAccess Time from CAS Precharge(15)EDO Page Mode READ-WRITECycle Time(24)
Data Output Hold after CASLOWOutput Buffer Turn-Off Delay fromCAS or RAS(13,15,19, 29)
Output Disable Delay from WELast CAS going LOW to First CASreturning HIGH(23)
CAS Setup Time (CBR REFRESH)(30, 20)CAS Hold Time (CBR REFRESH)(30, 21)OE Setup Time prior to RAS duringHIDDEN REFRESH CycleRefresh Period (512 Cycles)Transition Time (Rise or Fall)(2, 3)
35
Min.Max.15806804525301235—4053310880—1
—————————100K21——1515————850
-50Min.Max.1510081257034422050—47533101010081
—————————100K27——1515—————50
-60Min.Max.15150101408036492550—56533101010081
—————————100K34——1515—————50
Unitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsmsns
AC TEST CONDITIONS
Output load:
Two TTL Loads and 50 pF (Vcc = 5.0V ±10%)One TTL Load and 50 pF (Vcc = 3.3V ±10%)
Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V ±10%);
VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V ±10%)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5V ±10%, 3.3V ±10%)
Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
9
元器件交易网www.cecb2b.com
IC41C4100IC41LV4100
Notes:
1.An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.2.VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH
and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3.In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH)
in a monotonic manner.
4.If CAS and RAS = VIH, data output is High-Z.
5.If CAS = VIL, data output may contain data from the last valid READ cycle.6.Measured with a load equivalent to one TTL gate and 50 pF.
7.Assumes that tRCD ≤ tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase
by the amount that tRCD exceeds the value shown.8.Assumes that tRCD ≥ tRCD (MAX).
9.If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the
data output buffer, CAS and RAS must be pulsed for tCP.
10.Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD
is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11.Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD
is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.12.Either tRCH or tRRH must be satisfied for a READ cycle.
13.tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
14.tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS ≥ tWCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD ≥ tRWD(MIN), tAWD ≥ tAWD (MIN) and tCWD ≥ tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read fromthe selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go backto VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.15.Output parameter (I/O) is referenced to corresponding CAS input.
16.During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE
WRITE or READ-MODIFY-WRITE is not possible.17.Write command is defined as WE going low.
18.LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOWand OE is taken back to LOW after tOEH is met.
19.The I/Os are in open during READ cycles once tOD or tOFF occur.20.The first χCAS edge to transition LOW.21.The last χCAS edge to transition HIGH.
22.These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-MODIFY-WRITE cycles.
23.Last falling χCAS edge to first rising χCAS edge.
24.Last rising χCAS edge to next cycle’s last rising χCAS edge.25.Last rising χCAS edge to first falling χCAS edge.26.Each χCAS must meet minimum pulse width.27.Last χCAS to go LOW.
28.I/Os controlled, regardless CAS.
29.The 3 ns minimum is a parameter guaranteed by design.30.Enables on-chip refresh and address counters.
10Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
元器件交易网www.cecb2b.com
IC41C4100IC41LV4100
READ CYCLE
tRCtRAStRPRAStCSHtCRPtRCDtRSHtCAStCLCHtRRHCAStARtRADtASRtRAHtASCtRALtCAHADDRESSWERowtRCSColumntRCHtAAtRACtCACtCLZtOFF(1)RowI/OOEOpentOEValid DatatODOpentOESUndefinedDon’t CareNote:
1.tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
11
元器件交易网www.cecb2b.com
IC41C4100IC41LV4100
EARLY WRITE CYCLE (OE = DON'T CARE)
tRCtRAStRPRAStCSHtCRPtRCDtRSHtCAStCLCHCAStARtRADtASRtRAHtASCtRALtCAHtACHADDRESSRowColumntCWLtRWLtWCRtWCStWCHtWPRowWEtDHRtDStDHI/OValid DataDon’t Care12Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
元器件交易网www.cecb2b.com
IC41C4100IC41LV4100
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
tRWCtRAStRPRAStCSHtCRPtRCDtRSHtCAStCLCHCAStARtRADtASRtRAHtASCtCAHtACHtRALADDRESSRowtRCSColumntRWDtCWDtAWDRowtCWLtRWLtWPWEtAAtRACtCACtCLZtDStDHI/OOpentOEValid DOUTtODValid DINOpentOEHOEUndefinedDon’t CareIntegrated Circuit Solution Inc.
DR027-0A 09/05/2001
13
元器件交易网www.cecb2b.com
IC41C4100IC41LV4100
EDO-PAGE-MODE READ CYCLE
tRASPtRPRAStCSHtCRPtRCDtCAS, tCLCHtPC(1)tCAS, tCPtCLCHtRSHtCPtCAS, tCLCHtCPCAStARtRADtASRtASCtCAHtASCtCAHtASCtRALtCAHADDRESSRowtRAHtRCSColumnColumnColumntRCHRowtRRHWEtAAtRACtCACtCLZtCACtCOHtAAtCPAtCACtCLZtAAtCPAtOFFI/OOpentOEtOESValid DataValid DatatOEHCtODtOESValid DatatOEOpentODOEtOEPUndefinedDon’t CareNote:
1.tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Bothmeasurements must meet the tPC specifications.
14Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
元器件交易网www.cecb2b.com
IC41C4100IC41LV4100
EDO-PAGE-MODE EARLY-WRITE CYCLE
tRASPtRPRAStCSHtCRPtRCDtCAS, tCLCHtCPtPCtCAS, tCLCHtCPtRSHtCAS, tCLCHtACHtRALtCAHtCPCAStARtRADtASRtASCtACHtCAHtASCtACHtCAHtASCADDRESSRowtRAHColumntCWLtWCStWCHtWPColumntCWLtWCStWCHtWPColumntCWLtWCStWCHtWPRowWEtWCRtDHRtDStDHtDStDHtDStDHtRWLI/OOEValid DataValid DataValid DataDon’t CareIntegrated Circuit Solution Inc.
DR027-0A 09/05/2001
15
元器件交易网www.cecb2b.com
IC41C4100IC41LV4100
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles)
tRASPtRPRAStCSHtCRPtRCDtCAS, tCLCHtCPtPC / tPRWC(1)tCAS, tCLCHtCPtRSHtCAS, tCLCHtCPCAS tASRtRAHtARtRADtASCtRALtCAHtASCtCAHtASCtCAHADDRESSRowtRWDtRCSColumntCWLtWPtAWDtCWDColumntCWLtWPtAWDtCWDColumntRWLtCWLtWPtAWDtCWDRowWEtRACtCACtCLZ tAAtDStDHtAAtCPAtCACtCLZ tDStDHtAAtCPAtCACtCLZ tDHtDSI/OOpentOE DOUTDINtOD tOE DOUTDINtOD tOE DOUTDINtOD tOEH OpenOEUndefinedDon’t CareNote:
1.tPC is for LATE write cycles only. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge ofCAS to rising edge of CAS. Both measurements must meet the tPC specifications.
16Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
元器件交易网www.cecb2b.com
IC41C4100IC41LV4100
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY WRITE)
tRASPtRPRAStCSHtPCtCRPtRCDtCAStCPtCAS tPC tCPtRSHtCAStCPCAS tASRtRAHtARtRADtASCtACHtRALtCAHtCAHtASCtCAHtASCADDRESSRowtRCSColumn (A)Column (B)tRCHtWCSColumn (N) tWCHRowWEtRACtCACtAAtCPAtCACtCOH tAAtWHZtDStDHI/OOpentOE Valid Data (A)Valid Data (B)DINOpenOEDon’t CareIntegrated Circuit Solution Inc.
DR027-0A 09/05/2001
17
元器件交易网www.cecb2b.com
IC41C4100IC41LV4100
AC WAVEFORMS
READ CYCLE (With WE-Controlled Disable)
RAStCSHtCRPtRCDtCAStCPCAStARtRADtASRtRAHtASCtCAHtASCADDRESSWERowtRCSColumntRCHtAAtRACtCACtCLZtWPZColumntRCStWHZtCLZI/OOEOpentOEValid DataOpentODUndefinedDon’t CareRAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)
tRCtRAStRPRAStCRPtRPCCAStASRtRAHADDRESSI/ORowOpenRowDon’t Care18Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
元器件交易网www.cecb2b.com
IC41C4100IC41LV4100
CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)
tRPtRAStRPtRASRAStRPCtCPtCHRtCSRtRPCtCSRtCHRCASI/OOpenHIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW)
tRAStRPtRASRAStCRPtRCDtRSHtCHRCAStARtASRtRADtRAHtASCtRALtCAHADDRESSRowColumntAAtRACtCACtCLZtOFF(2)I/OOpentOEtORDValid DataOpentODOEUndefinedDon’t CareNotes:
1.A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.2.tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
19
元器件交易网www.cecb2b.com
IC41C4100IC41LV4100
ORDERING INFORMATIONIC41C4100
Commercial Range: 0°C to 70°C
Speed (ns)Order Part No.
355060
IC41C4100-35JIS41C4100-35TIC41C4100-50JIC41C4100-50TIC41C4100-60JIC41C4100-60T
PacJage300mil SOJ300mil TSOP-2300mil SOJ300mil TSOP-2300mil SOJ300mil TSOP-2
ORDERING INFORMATION:IC41LV4100
Commercial Range: 0°C to 70°C
Speed (ns)Order Part No.
355060
IC41LV4100-35JIC41LV4100-35TIC41LV4100-50JIC41LV4100-50TIC41LV4100-60JIC41LV4100-60T
Package300mil SOJ300mil TSOP-2300mil SOJ300mil TSOP-2300mil SOJ300mil TSOP-2
Industrial Range: -40°C to 85°C
Speed (ns)Order Part No.
355060
IC41C4100-35JIIC41C4100-35TIIC41C4100-50JIIC41C4100-50TIIC41C4100-60JIIC41C4100-60TI
Package300mil SOJ300mil TSOP-2300mil SOJ300mil TSOP-2300mil SOJ300mil TSOP-2
Industrial Range: -40°C to 85°C
Speed (ns)Order Part No.
355060
IC41LV4100-35JIC41LV4100-35TIC41LV4100-50JIIC41LV4100-50TIIC41LV4100-60JIIC41LV4100-60TI
Package300mil SOJ300mil TSOP-2300mil SOJ300mil TSOP-2300mil SOJ300mil TSOP-2
20Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
元器件交易网www.cecb2b.com
IC41C4100IC41LV4100
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140FAX: 886-2-26962252http://www.icsi.com.tw
Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
21
因篇幅问题不能全部显示，请点此查看更多更全内容