EDA数字钟程序代码

use ieee.std_logic_1164.all; entity fenpin is port(clk:in std_logic; qH: buffer std_logic; qout:buffer std_logic); end entity;

architecture c20 of fenpin is begin process(clk)

variable num : integer :=1; variable num1 : integer :=1 begin

if clk'event and clk='0' then

if(num=2)--0000000) --1HZ--10000000 to timer then num:=1;qout<=not qout; else

num:=num+1; end if;

if(num1=1)--000000) --1000HZ--10000 to wei then num1:=1;qH<=not qH; else

num1:=num1+1; end if; end if; end process; end c20; --timer library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity Clock3 is port(clk:in std_logic;

duan: out std_logic_vector(3 downto 0); wei: in std_logic_vector(2 downto 0); wei2: out std_logic_vector(2 downto 0) ); end entity;

architecture clo of Clock3 is signal clk2:std_logic ;

signal keys: std_logic_vector(2 downto 0); begin

keys<=key_h&key_m&key_s; clk2<=clk or flag;

process(key_que) begin

if key_que'event and key_que='0' then flag<= not flag; end if; end process;

process(clk2,keys)--如果用拨码开关，就将clk2 改为clk begin case flag is when '0' =>

if clk2'event and clk2='0' then ---正常计时

if scn=59 and min=59 and hor=23 then scn:=0;min:=0;hor:=0; elsif scn=59 and min=59

then scn:=0;min:=0;hor:=hor+1; elsif scn=59

then scn:=0;min:=min+1; else scn:=scn+1; end if;

if min=59 ---整点报时500hz

then if scn=50 or scn=52 or scn=54 or scn=56 or scn=58 then music_out<=musicL; else music_out<='0'; end if;

elsif min=0 and scn=0---整点报时1000HZ then music_out<=musicH; else music_out<='0'; end if; end if; when '1' => case keys is when \"011\" => if hor=23 then hor:=0; else hor:=hor+1; end if; --keys<=\"00\"; when \"101\" => if min=59

then min:=0; else min:=min+1; end if; -- keys<=\"00\"; when \"110\" => if scn=59 then scn:=0; else scn:=scn+1; end if; -- keys<=\"00\";

when others => null;-- keys<=\"00\"; end case; end case;

h:=hor/10; --除法，特别是取余数运算会占用很多逻辑资源 hH<=\"0000\"+h; hL<=\"0000\"+(hor-10*h); m:=min/10; mH<=\"0000\"+m; mL<=\"0000\"+(min-10*m); s:=scn/10; sH<=\"0000\"+s; sL<=\"0000\"+(scn-10*s); end process; end clo; 去抖

library ieee;--去抖电路 use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity qudou is

port( clk,key_in:in std_logic; key_out:out std_logic); end entity;

architecture key_qudou of qudou is begin

process(clk)--5ms

variable num: integer :=0; variable s: integer :=0; begin

if clk'event and clk='0' then case s is when 0 => key_out<='1'; if key_in='0'

then num:=num+1;--用状态机思路更清晰，但是程序体积更庞大 if num=3

then num:=0;s:=1; end if; else num:=0; end if; when 1 => key_out<='0'; if key_in='1' then s:=0; end if;

when others=> null; end case; end if; end process; key_qudou; --顶层文件

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity Clock is port( clk:in std_logic;

music_out:out std_logic; key_in:in std_logic; keyh_in:in std_logic; keym_in:in std_logic; keys_in:in std_logic;

duan: out std_logic_vector(6 downto 0); wei: buffer std_logic_vector(2 downto 0)); end entity;

architecture clo of Clock is component fenpin port(clk:in std_logic;

musicH: buffer std_logic; musicL: buffer std_logic; qH: buffer std_logic; qM: buffer std_logic; qout:buffer std_logic); end component;

component counter_8 port( clk: in std_logic;

count: buffer std_logic_vector(2 downto 0));

end component;

component Clock3 port(clk:in std_logic; key_que:in std_logic; key_h:in std_logic; key_m:in std_logic; key_s:in std_logic; musicH:in std_logic; musicL:in std_logic; music_out:out std_logic;

duan: out std_logic_vector(3 downto 0); wei: in std_logic_vector(2 downto 0); wei2: out std_logic_vector(2 downto 0) ); end component;

component seg7dec

port( din: in std_logic_vector(3 downto 0);

qout:out std_logic_vector(6 downto 0));--a,b,c...f,g end component;

component qudou

port( clk,key_in:in std_logic; keyh_in:in std_logic; keym_in:in std_logic; keys_in:in std_logic; key_out:out std_logic; keyh_out:out std_logic; keym_out:out std_logic; keys_out:out std_logic); end component; begin

u1: fenpin port map(clk=>clk,qH=>clkH,qout=>clkL,qM=>clkM,musicH=>c_m_H,musicL=>c_m_L); u2: counter_8 port map(clk=>clkH,count=>wei_in); u3: seg7dec port map(din=>duan_in,qout=>duan); u4:

Clock3

port

map(clk=>clkL,duan=>duan_in,wei=>wei_in,wei2=>wei,key_que=>key0,key_h=>key1,key_m=>key2,key_s=>key3,musicH=>c_m_H,musicL=>c_m_L,music_out=>music_out); u5:

_out=>key1,keym_out=>key2,keys_out=>key3); end clo;

qudou

port

map(clk=>clkM,key_in=>key_in,keyh_in=>keyh_in,keym_in=>keym_in,keys_in=>keys_in,key_out=>key0,keyh