CAT25C128/256CAT25C128/256128K/256K-Bit SPI Serial CMOS EEPROMFEATURESI 5 MHz SPI CompatibleI1.8 to 5.5 Volt OperationIHardware and Software ProtectionILow Power CMOS TechnologyISPI Modes (0,0 &1,1)IIndustrial and AutomotiveISelf-Timed Write CycleI64-Byte Page Write BufferIBlock Write Protection– Protect 1/4, 1/2 or all of EEPROM ArrayI100,000 Program/Erase CyclesI100 Year Data RetentionIRoHS-compliant packagesTemperature RangesDESCRIPTIONThe CAT25C128/256 is a 128K/256K-Bit SPI SerialCMOS EEPROM internally organized as 16Kx8/32Kx8bits. Catalyst’s advanced CMOS Technologysubstantially reduces device power requirements. TheCAT25C128/256 features a 64-byte page write buffer.The device operates via the SPI bus serial interfaceand is enabled through a Chip Select (CS). In additionto the Chip Select, the clock input (SCK), data in (SI)and data out (SO) are required to access the device.The HOLD pin may be used to suspend any serialcommunication without resetting the serial sequence.The CAT25C128/256 is designed with software andhardware write protection features including Block Lockprotection. The device is available in 8-pin DIP, 8-pinSOIC, 14-pin TSSOP and 20-pin TSSOP packages.PIN CONFIGURATIONSOIC Package(V**, X)CSSOWPVSS12348765VCCHOLDSCKSIBLOCK DIAGRAM1234567141312111098TSSOP Package (Y14)**CSSONCNCNCWPVSSVCCHOLDNCNCNCSCKSISENSE AMPSSHIFT REGISTERSWORD ADDRESSBUFFERSSOSICSWPHOLDSCKCOLUMNDECODERSDIP Package (L)CSSOWPSS12348765VCCHOLDSCKSITSSOP Package (Y20)**NCCSSOSONCNCWPVSSNCNC1234567891020191817161514131211**CAT25C128 only.PIN FUNCTIONSPin NameSOSCKWPVCCVSSCSSIHOLDNCNCVCCHOLDHOLDNCNCSCKSINCNCI/OCONTROLSPICONTROLLOGICBLOCKPROTECTLOGICCONTROL LOGICXDECEEPROMARRAYFunctionSerial data OutputSerial ClockWrite ProtectPower SupplyGroundChip SelectSerial Data InputSuspends Serial InputNo Connect1
DATA INSTORAGEHIGH VOLTAGE/TIMING CONTROLSTATUSREGISTERFor Ordering Information details, see page 11.© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Document No. 1018, Rev. I
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CAT25C128/256
ABSOLUTE MAXIMUM RATINGS*Temperature Under Bias.................–55°C to +125°CStorage Temperature.......................–65°C to +150°CVoltage on any Pin withRespect to VSS1)...................–2.0V to +VCC +2.0VVCC with Respect to VSS................................–2.0V to +7.0VPackage Power DissipationCapability (Ta = 25°C)...................................1.0WLead Soldering Temperature (10 secs)............300°COutput Short Circuit Current(2)........................100 mARELIABILITY CHARACTERISTICSSymbolNEND(3)TDR(3)VZAP(3)ILTH(3)(4)ParameterEnduranceData RetentionESD SusceptibilityLatch-UpMin.100,0001002000100Max.UnitsCycles/ByteYearsVoltsmA*COMMENTStresses above those listed under “Absolute MaximumRatings” may cause permanent damage to the device.These are stress ratings only, and functional operationof the device at these or any other conditions outside ofthose listed in the operational sections of this specificationis not implied. Exposure to any absolute maximum ratingfor extended periods may affect device performanceand reliability.D.C. OPERATING CHARACTERISTICSVCC = +1.8V to +5.5V, unless otherwise specified.LimitsSymbolICC1ICC2ISB(5)ILIILOVIL(3)VIH(3)VOL1VOH1VOL2VOH2ParameterPower Supply Current(Operating Write)Power Supply Current(Operating Read)Power Supply Current(Standby)Input Leakage CurrentOutput Leakage CurrentInput Low VoltageInput High VoltageOutput Low VoltageOutput High VoltageOutput Low VoltageOutput High VoltageVCC-0.2VCC - 0.80.2-1VCC x 0.7Min.Typ.Max.102123VCC x 0.3VCC + 0.50.4UnitsmAmAµAµAµAVVVVVV4.5V≤VCC<5.5VIOL = 3.0mAIOH = -1.6mA1.8V≤VCC<2.7VIOL = 150µAIOH = -100µAVOUT = 0V to VCC,CS = 0VTest ConditionsVCC = 5V @ 5MHzSO=open; CS=VssVCC = 5.0VFCLK = 5MHzCS = VCCVIN = VSS or VCCNote:(1)The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DCvoltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.(2)Output shorted for no more than one second. No more than one output shorted at a time.(3)This parameter is tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 andJEDEC test methods.(4)Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.(5)Maximum standby current (ISB ) = 10µA for the Automotive and Extended Automotive temperature range.Document No. 1018, Rev. I
2
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CAT25C128/256
PIN CAPACITANCE (1)Applicable over recommended operating range from TA=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).SymbolCOUTCINTest ConditionsOutput Capacitance (SO)Input Capacitance (CS, SCK, SI, WP, HOLD)Max.86UnitspFpFConditionsVOUT=0VVIN=0VA.C. CHARACTERISTICS (CAT25C128)LimitsVcc=1.8V-5.5VSYMBOLPARAMETERtSUtHtWHtWLfSCKtLZtRI(1)tFI(1)tHDtCDtWCtVtHOtDIStHZtCStCSStCSHtWPStWPHData Setup TimeData Hold TimeSCK High TimeSCK Low TimeClock FrequencyHOLD to Output Low ZInput Rise TimeInput Fall TimeHOLD Setup TimeHOLD Hold TimeWrite Cycle TimeOutput Valid from Clock LowOutput Hold TimeOutput Disable TimeHOLD to Output High ZCS High TimeCS Setup TimeCS Hold TimeWP Setup TimeWP Hold Time100010005005050025015025025025050502502501025002501502001001005050Min.100100250250DC1502225025010250010050Max.VCC=2.5V-5.5VMin.7070 150150DC350224040580Max.VCC =4.5V-5.5VMin.35358080DC55022Max.nsnsnsnsMHznsµsµsnsnsmsnsnsnsnsnsnsnsnsnsCL = 50pFTestUNITSConditionsNOTE:(1) This parameter is tested initially and after a design or process change that affects the parameter.3Document No. 1018, Rev. I
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CAT25C128/256
A.C. CHARACTERISTICS (CAT25C256)LimitsVcc=1.8V-5.5VSYMBOLPARAMETERtSUtHtWHtWLfSCKtLZtRI(3)tFI(3)tHDtCDtWCtVtHOtDIStHZtCStCSStCSHtWPStWPHData Setup TimeData Hold TimeSCK High TimeSCK Low TimeClock FrequencyHOLD to Output Low ZInput Rise TimeInput Fall TimeHOLD Setup TimeHOLD Hold TimeWrite Cycle TimeOutput Valid from Clock LowOutput Hold TimeOutput Disable TimeHOLD to Output High ZCS High TimeCS Setup TimeCS Hold TimeWP Setup TimeWP Hold Time10010010050500250150100100100505025025010250050050025002500DC0.21002210010010200020010010010010050501001001005050VCC=2.5V-5.5V100100250250DC2.05022VCC =2.7V-5.5V7070150150DC2.5502210010010200VCC=4.5V-5.5V35358080DC550224040580010050nsnsnsnsMHznsµsµsnsnsmsnsnsnsnsnsnsnsnsnsTestMin.Max.Min.Max.Min.Max.Min.Max.UNITSConditionsCL = 50pF 200100NOTE:(3) This parameter is tested initially and after a design or process change that affects the parameter.Document No. 1018, Rev. I4
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CAT25C128/256
FUNCTIONAL DESCRIPTIONThe CAT25C128/256 supports the SPI bus datatransmission protocol. The synchronous Serial PeripheralInterface (SPI) helps the CAT25C128/256 to interfacedirectly with many of today’s popular microcontrollers.The CAT25C128/256 contains an 8-bit instructionregister. (The instruction set and the operation codesare detailed in the instruction set table)After the device is selected with CS going low, the firstbyte will be received. The part is accessed via the SI pin,with data being clocked in on the rising edge of SCK.The first byte contains one of the six op-codes that definethe operation to be performed.SO: Serial OutputSO is the serial data output pin. This pin is used to transferdata out of the CAT25C128/256. During a read cycle, datais shifted out on the falling edge of the serial clock.SCK: Serial ClockSCK is the serial clock pin. This pin is used to synchronizethe communication between the microcontroller and theCAT25C128/256. Opcodes, byte addresses, or datapresent on the SI pin are latched on the rising edge of theSCK. Data on the SO pin is updated on the falling edge ofthe SCK.CS: Chip SelectCS is the Chip select pin. CS low enables the CAT25C128/256 and CS high disables the CAT25C128/256. CS hightakes the SO output pin to high impedance and forces thedevices into a Standby Mode (unless an internal writeoperation is underway). The CAT25C128/256 drawsZERO current in the Standby mode. A high to low transitionon CS is required prior to any sequence being initiated. Alow to high transition on CS after a valid write sequence iswhat initiates an internal write cycle.PIN DESCRIPTIONSI: Serial InputSI is the serial data input pin. This pin is used to input allopcodes, byte addresses, and data to be written to the25C32/64. Input data is latched on the rising edge of theserial clock.Figure 1.Sychronous Data TimingVIHtCSCSVILtCSSVIHVILtSUVIHtCSHSCKtWHtHtWLSIVILVALID INtRItFItVtHOtDISHI-ZSOVOHVOLHI-ZNote: Dashed Line= mode (1, 1) — ———INSTRUCTION SET Instruction WREN WRDI RDSR WRSR READ WRITEOpcode0000 01100000 01000000 01010000 00010000 00110000 0010OperationEnable Write OperationsDisable Write OperationsRead Status RegisterWrite Status RegisterRead Data from MemoryWrite Data to Memory5Document No. 1018, Rev. I
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CAT25C128/256
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin willallow normal read/write operations when held high.When WP is tied low and the WPEN bit in the statusregister is set to “1”, all write operations to the statusregister are inhibited. WP going low while CS is still lowwill interrupt a write to the status register. If the internalwrite cycle has already been initiated, WP going low willhave no effect on any write operation to the statusregister. The WP pin function is blocked when the WPENbit is set to 0.
HOLD: Hold
The HOLD pin is used to pause transmission to theCAT25C128/256 while in the middle of a serial sequencewithout having to re-transmit entire sequence at a latertime. To pause, HOLD must be brought low while SCK islow. The SO pin is in a high impedance state during thetime the part is paused, and transitions on the SI pins willbe ignored. To resume communication, HOLD is broughthigh, while SCK is low. (HOLD should be held high anytime this function is not being used.) HOLD may be tiedhigh directly to Vcc or tied to Vcc through a resistor. FigureSTATUS REGISTER
7WPEN
6X
5X
4X
3BP1
2BP0
1WEL
0RDY
9 illustrates hold timing sequence.
STATUS REGISTER
The Status Register indicates the status of the device.The RDY (Ready) bit indicates whether the CAT25C128/256 is busy with a write operation. When set to 1 a writecycle is in progress and when set to 0 the deviceindicates it is ready. This bit is read only.
The WEL (Write Enable) bit indicates the status of thewrite enable latch . When set to 1, the device is in a WriteEnable state and when set to 0 the device is in a WriteDisable state. The WEL bit can only be set by the WRENinstruction and can be reset by the WRDI instruction.The BP0 and BP1 (Block Protect) bits indicate whichblocks are currently protected. These bits are set by theuser issuing the WRSR instruction. The user is allowedto protect quarter of the memory, half of the memory orthe entire memory by setting these bits. Once protectedthe user may only read from the protected portion of thearray. These bits are non-volatile.
BLOCK PROTECTION BITS
Status Register BitsBP1BP00011
0101
Array Address
Protected
None
25C128: 3000-3FFF 25C256: 6000-7FFF25C128: 2000-3FFF 25C256: 4000-7FFF25C128: 0000-3FFF 25C256: 0000-7FFF
ProtectionNo ProtectionQuarter Array ProtectionHalf Array ProtectionFull Array Protection
WRITE PROTECT ENABLE OPERATION
ProtectedBlocksProtectedProtectedProtectedProtectedProtectedProtected
6
WPEN0011XX
WPXXLowLowHighHigh
WEL010101
UnprotectedBlocksProtectedWritableProtectedWritableProtectedWritable
StatusRegisterProtectedWritableProtectedProtectedProtectedWritable
Document No. 1018, Rev. I
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CAT25C128/256
The WPEN (Write Protect Enable) is an enable bit for theWP pin. The WP pin and WPEN bit in the status registercontrol the programmable hardware write protect fea-ture. Hardware write protection is enabled when WP islow and WPEN bit is set to high. The user cannot writeto the status register (including the block protect bits andthe WPEN bit) and the block protected sections in thememory array when the chip is hardware write pro-tected. Only the sections of the memory array that arenot block protected can be written. Hardware writeprotection is disabled when either WP pin is high or theWPEN bit is zero.
latch) to the device. Disabling writes will protect thedevice against inadvertent writes.
READ Sequence
The part is selected by pulling CS low. The 8-bit readinstruction is transmitted to the CAT25C128/256, followedby the 16-bit address(the three Most Significant Bit isdon’t care for 25C256 and four most significant bits aredon't care for 25C128).
After the correct read instruction and address are sent,the data stored in the memory at the selected address isshifted out on the SO pin. The data stored in the memoryat the next address can be read sequentially by continuingto provide clock pulses. The internal address pointer isautomatically incremented to the next higher addressafter each byte of data is shifted out. When the highestaddress (7FFFh for 25C256 and 3FFFh for 25C128) isreached, the address counter rolls over to 0000h allowingthe read cycle to be continued indefinitely. Thereadoperation is terminated by pulling the CS high.
DEVICE OPERATION
Write Enable and Disable
The CAT25C128/256 contains a write enable latch. Thislatch must be set before any write operation. The devicepowers up in a write disable state when Vcc is applied.WREN instruction will enable writes (set the latch) to thedevice. WRDI instruction will disable writes (reset theFigure 2. WREN Instruction Timing
CSSKSI00000110SOHIGH IMPEDANCEFigure 3. WRDI Instruction Timing
CSSKSI00000100SONote: Dashed Line= mode (1, 1) — ———HIGH IMPEDANCE7Document No. 1018, Rev. I
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CAT25C128/256
To read the status register, RDSR instruction should besent. The contents of the status register are shifted outon the SO line. The status register may be read at anytime even during a write cycle. Read sequece is illus-trated in Figure 4. Reading status register is illustrated inFigure 5.WRITE SequenceThe CAT25C128/256 powers up in a Write Disablestate. Prior to any write instructions, the WREN instruc-tion must be sent to CAT25C128/256. The device goesinto Write enable state by pulling the CS low and thenclocking the WREN instruction into CAT25C128/256.The CS must be brought high after the WREN instructionto enable writes to the device. If the write operation isinitiated immediately after the WREN instruction withoutCS being brought high, the data will not be written to thearray because the write enable latch will not have beenFigure 4. Read Instruction TimingCS0SKOPCODE properly set. Also, for a successful write operation theaddress of the memory location(s) to be programmedmust be outside the protected address field locationselected by the block protection level.Byte WriteOnce the device is in a Write Enable state, the user mayproceed with a write sequence by setting the CS low,issuing a write instruction via the SI line, followed by the16-bit address (the three Most Significant Bits are don’tcare for 25C256 and four most significant bits are don'tcare for 25C128), and then the data to be written.Programming will start after the CS is brought high. Figure6 illustrates byte write sequence.During an internal write cycle, all commands will beignored except the RDSR (Read Status Register)instruction.123456789102021222324252627282930SI00000011BYTE ADDRESS*DATA OUTSOHIGH IMPEDANCE7MSB6543210*Please check the instruction set table for addressNote: Dashed Line= mode (1, 1) — ———Figure 5. RDSR TimingCS0SCKOPCODE1234567891011121314SI00000101DATA OUTSOHIGH IMPEDANCE7MSB6543210Note: Dashed Line= mode (1, 1) — ———Document No. 1018, Rev. I8
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CAT25C128/256
The Status Register can be read to determine if the writecycle is still in progress. If Bit 0 of the Status Register isset at 1, write cycle is in progress. If Bit 0 is set at 0, thedevice is ready for the next instruction.
Page Write
The CAT25C128/256 features page write capability.After the first initial byte the host may continue to writeup to 64 bytes of data to the CAT25C128/256. Aftereach byte of data is received, six lower order addressbits are internally incremented by one; the high orderbits of address will remain constant. The only restrictionis that the 64 bytes must reside on the same page. If theFigure 6. Write Instruction Timing
CS0SKOPCODEDATA INaddress counter reaches the end of the page and clockcontinues, the counter will “roll over” to the first addressof the page and overwrite any data that may have beenwritten. The CAT25C128/256 is automatically returnedto the write disable state at the completion of the writecycle. Figure 8 illustrates the page write sequence.To write to the status register, the WRSR instructionshould be sent. Only Bit 2, Bit 3 and Bit 7 of the statusregister can be written using the WRSR instruction.Figure 7 illustrates the sequence of writing to statusregister.
12345678212223242526272829303SI00000010ADDRESSD7D6D5D4D3D2D1D0SOHIGH IMPEDANCENote: Dashed Line= mode (1, 1) — ———Figure 7. WRSR Timing
CS0SCKOPCODE123456789101112131415DATA INSI000000017MSB6543210SOHIGH IMPEDANCENote: Dashed Line= mode (1, 1) — ———Figure 8. Page Write Instruction Timing
CS0SKOPCODEDATA IN1234567821222324-3132-3924+(N-1)x8-1..24+(N-1)x824+Nx8-1SI00000010ADDRESSDataByte 1DataByte 2DataByte 3Data Byte N07..1SONote: Dashed Line= mode (1, 1) — ———HIGH IMPEDANCE9Document No. 1018, Rev. I
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CAT25C128/256
DESIGN CONSIDERATIONSThe CAT25C128/256 powers up in a write disable stateand in a low power standby mode. A WREN instructionmust be issued to perform any writes to the device afterpower up. Also,on power up CS should be brought lowto enter a ready state and receive an instruction. Aftera successful byte/page write or status register write theCAT25C128/256 goes into a write disable mode. CSmust be set high after the proper number of clock cyclesto start an internal write cycle. Access to the array duringan internal write cycle is ignored and program-mingis continued. On power up, SO is in a high impedance.Figure 9. HOLD TimingCStCDSCKtHDHOLDtHZSOHIGH IMPEDANCEIf an invalid op code is received, no data will be shiftedinto the CAT25C128/256, and the serial output pin (SO)will remain in a high impedence state until the fallingedge of CS is detected again.When powering down, the supply should be taken downto 0V, so that the CAT25C128/256 will be reset whenpower is ramped back up. If this is not possible, then,following a brown-out episode, the CAT25C128/256can be reset by refreshing the contents of the StatusRegister (See Application Note AN10).tCDtHDtLZNote: Dashed Line= mode (1, 1) — ———Figure 10. WP TimingtWPStWPHtCSHSCKWPNote: Dashed Line= mode (1, 1) — ———Document No. 1018, Rev. I10
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CAT25C128/256
ORDERING INFORMATIONPrefixCATOptionalCompany IDDevice #25C128ProductNumber25C128: 128K25C256: 256KVSuffixITemperature RangeI = Industrial (-40˚C to +85˚C)A = Automotive (-40˚C to +105˚C)E = Extended (-40˚C to +125˚C)PackageL: PDIPV: SOIC, JEDEC**X: SOIC, EIAJ(4)Y14: 14-Pin TSSOP**Y20: 20-Pin TSSOP****CAT25C128 only- 1.8– GT3 Tape & ReelT: Tape & Reel2: 2000/Reel3: 3000/Reel Lead Finish Blank: Matte-Tin G: NiPdAuOperating VoltageBlank (VCC = 2.5V to 5.5V1.8 (VCC = 1.8V to 5.5V)Notes:(1) All packages are RoHS-compliant (Lead-free, Halogen-free).(2) The standard finish is NiPdAu pre-plated (PPF).(3) The device used in the above example is a CAT25C128VI-1.8-GT3 (SOIC, Industrial Temperature, 1.8V to 5.5V Operating Voltage,NiPdAu, Tape & Reel).(4)For SOIC, EIAJ (X) package the standard finish is Matte-Tin. This package is available in 2000 pcs/reel, i.e. CAT25C256XI-T2.(5) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.11Document No. 1018, Rev. I
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CAT25C128/256REVISION HISTORYDate8/5/20042/17200505/23/200510/13/06Rev.FGHIReasonUpdated FeaturesUpdated DC Operating Characteristics table & notesUpdated D.C. Operating Characteristics tableUpdated Reliability Characteristics tableUpdate FeaturesUpdate DescriptionUpdate Pin ConfigurationUpdate Pin FuntionsUpdate D.C. Operating Characteristics (VCC Range)Update A.C. Characteristics tables (VCC Range)Update Ordering InformationCopyrights, Trademarks and PatentsTrademarks and registered trademarks of Catalyst Semiconductor include each of the following:DPP ™DPPs ™AE2 ™Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patentsissued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITSPRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THERIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISINGOUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, orother applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create asituation where personal injury or death may occur.Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheetslabeled \"Advance Information\" or \"Preliminary\" and other products described herein may not be in production or offered for sale.Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustratetypical semiconductor applications and may not be complete.Catalyst Semiconductor, Inc.Corporate Headquarters2975 Stender WaySanta Clara, CA 95054Phone: 408.542.1000Fax: 408.542.1200www.catsemi.comDocument No. 1018, Rev. IPublication #:Revison:Issue date:Type:121018I10/13/06Final
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