Preliminary
CAT24WC256
256K-Bit I2C Serial CMOS E2PROMFEATURES
s1MHz I2C Bus Compatible*s1.8 to 6 Volt OperationsLow Power CMOS Technologys64-Byte Page Write Buffer
sSelf-Timed Write Cycle with Auto-ClearsCommercial, Industrial and Automotive
sWrite Protect Feature
– Entire Array Protected When WP at VIH
s100,000 Program/Erase Cycless100 Year Data Retentions8-Pin DIP or 8-Pin SOIC
Temperature Ranges
DESCRIPTION
The CAT24WC256 is a 256K-bit Serial CMOS E2PROMinternally organized as 32,768 words of 8 bits each.Catalyst’s advanced CMOS technology substantiallyreduces device power requirements. The
CAT24WC256 features a 64-byte page write buffer. Thedevice operates via the I2C bus serial interface and isavailable in 8-pin DIP or 8-pin SOIC packages.
PIN CONFIGURATION
DIP Package (P)
A0A1NCVSS12348765VCCWPSCLSDABLOCK DIAGRAM
EXTERNAL LOADDOUTACKVCCVSSWORD ADDRESSBUFFERSCOLUMNDECODERS512SENSE AMPSSHIFT REGISTERSSOIC Package (K)A0A1NCVSS12348765VCCWPSCLSDA24WC256 F01
SDASTART/STOPLOGICXDECWPCONTROLLOGIC512E2PROM512X512PIN FUNCTIONS
Pin Name A0, A1SDASCLWPVCCVSSNC
Function
Address InputsSerial Data/AddressSerial ClockWrite Protect
+1.8V to +6.0V Power SupplyGroundNo Connect
SCLA0A1STATE COUNTERSSLAVEADDRESSCOMPARATORS24WC256 F02
DATA IN STORAGEHIGH VOLTAGE/TIMING CONTROL* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25061-00 6/99 S-1
元器件交易网www.cecb2b.com
CAT24WC256
Preliminary
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias.................–55°C to +125°CStorage Temperature.......................–65°C to +150°CVoltage on Any Pin with
Respect to Ground(1)...........–2.0V to +VCC + 2.0VVCC with Respect to Ground...............–2.0V to +7.0VPackage Power Dissipation
Capability (Ta = 25°C)...................................1.0WLead Soldering Temperature (10 secs)............300°COutput Short Circuit Current(2)........................100mA RELIABILITY CHARACTERISTICSSymbolNEND(3)TDR(3)VZAP(3)ILTH(3)(4)
ParameterEnduranceData RetentionESD SusceptibilityLatch-up
Min.100,0001002000100
Max.
*COMMENT
Stresses above those listed under “Absolute MaximumRatings” may cause permanent damage to the device.These are stress ratings only, and functional operation ofthe device at these or any other conditions outside of thoselisted in the operational sections of this specification is notimplied. Exposure to any absolute maximum rating forextended periods may affect device performance andreliability.
UnitsCycles/ByteYearsVoltsmA
Reference Test MethodMIL-STD-883, Test Method 1033MIL-STD-883, Test Method 1008MIL-STD-883, Test Method 3015JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
Limits
Symbol Parameter ICC1 ICC2 ISB(5) ILI ILO VIL VIH VOL1 VOL2
Power Supply Current - ReadPower Supply Current - WriteStandby CurrentInput Leakage CurrentOutput Leakage CurrentInput Low VoltageInput High Voltage
Output Low Voltage (VCC = +3.0V)Output Low Voltage (VCC = +1.8V)
–1VCC x 0.7Min.
Typ. Max. 1
3
Units Test ConditionsmAmAµAµAµAVVVV
IOL = 3.0 mAIOL = 1.5 mAfSCL = 100 KHzVCC=5VfSCL = 100KHzVCC=5V
VIN = GND or VCCVCC=5V
VIN = GND to VCCVOUT = GND to VCC
0 1 1VCC x 0.3VCC + 0.5
0.4
0.5CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5VSymbolCI/O(3)CIN(3)
Test
Input/Output Capacitance (SDA)Input Capacitance (SCL, WP, A0, A1)
Max.86
UnitspFpF
ConditionsVI/O = 0VVIN = 0V
Note:
(1)The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.(2)Output shorted for no more than one second. No more than one output shorted at a time.
(3)This parameter is tested initially and after a design or process change that affects the parameter.
(4)Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.(5)Standby current (ISB ) = 0 µA (<900 nA).
Doc. No. 25061-00 6/99 S-1
2
元器件交易网www.cecb2b.com
Preliminary
A.C. CHARACTERISTICS
VCC = +1.8V to +6V, unless otherwise specifiedOutput Load is 1 TTL Gate and 100pFRead & Write Cycle LimitsSymbolParameterVCC=1.8V - 6.0VVCC=2.5V - 6.0VVCC=3.0V - 5.5VMin.FSCLtAAtBUF(2)tHD:STAtLOWtHIGHtSU:STAtHD:DATtSU:DATtR(2)tF(2)tSU:STOtDHtWRClock FrequencySCL Low to SDA Data Outand ACK OutTime the Bus Must be Free Beforea New Transmission Can StartStart Condition Hold TimeClock Low PeriodClock High PeriodStart Condition Setup Time(for a Repeated Start Condition)Data In Hold TimeData In Setup TimeSDA and SCL Rise TimeSDA and SCL Fall TimeStop Condition Setup TimeData Out Hold TimeWrite Cycle Time4.7100100.14.74.04.74.04.001001.03000.65010Max.1003.50.051.20.61.20.60.601000.33000.25505Min.Max.4000.90.050.50.250.60.40.2501000.3100Min.Max.10000.55UnitskHzµsµsµsµsµsµsnsnsµsnsµsnsmsCAT24WC256
Power-Up Timing (2)(3)SymboltPURtPUW
Parameter
Power-Up to Read OperationPower-Up to Write Operation
Max.11
Unitsmsms
Note:
(1) AC measurement conditions:
RL (connects to VCC): 0.3VCC to 0.7 VCC Input rise and fall times: < 50ns Input and output timing reference voltages: 0.5 VCC
(2)This parameter is tested initially and after a design or process change that affects the parameter.
(3)tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
The write cycle time is the time from a valid stopcondition of a write sequence to the end of the internalprogram/erase cycle. During the write cycle, the businterface circuits are disabled, SDA is allowed to remainhigh, and the device does not respond to its slaveaddress.
3
Doc. No. 25061-00 6/99 S-1
元器件交易网www.cecb2b.com
CAT24WC256
Preliminary
FUNCTIONAL DESCRIPTION
The CAT24WC256 supports the I2C Bus data transmis-sion protocol. This Inter-Integrated Circuit Bus protocoldefines any device that sends data to the bus to be atransmitter and any device receiving data to be a re-ceiver. The transfer is controlled by the Master devicewhich generates the serial clock and all START andSTOP conditions for bus access. The CAT24WC256operates as a Slave device. Both the Master device andSlave device can operate as either transmitter or re-ceiver, but the Master device controls which mode isactivated.
SDA: Serial Data/Address
The bidirectional serial data/address pin is used totransfer all data into and out of the device. The SDA pinis an open drain output and can be wire-ORed with otheropen drain or open collector outputs.
WP: Write Protect
This input, when tied to GND, allows write operations tothe entire memory. When this pin is tied to Vcc, theentire memory is write protected. When left floating,memory is unprotected.
A0, A1: Device Address Inputs
These pins are hardwired or left connected. Whenhardwired, up to four CAT24WC256's may be addressedon a single bus system. When the pins are left uncon-nected, the default values are zero.
PIN DESCRIPTIONSSCL: Serial Clock
The serial clock input clocks all data transferred into orout of the device.Figure 1. Bus TimingtFtLOWSCLtSU:STAtHD:STAtHD:DATtHIGHtRtLOWtSU:DATtSU:STOSDA INtAASDA OUT5020 FHD F03
tDHtBUFFigure 2. Write Cycle TimingSCLSDA8TH BITBYTE nACKtWRSTOPCONDITIONSTARTCONDITIONADDRESS5020 FHD F04
Figure 3. Start/Stop Timing
SDASCLSTART BITSTOP BIT5020 FHD F05
Doc. No. 25061-00 6/99 S-1
4
元器件交易网www.cecb2b.com
Preliminary
CAT24WC256
I2C BUS PROTOCOL
The features of the I2C bus protocol are defined asfollows:
(1)Data transfer may be initiated only when the bus is
not busy.(2)During a data transfer, the data line must remain
stable whenever the clock line is high. Any changesin the data line while the clock line is high will beinterpreted as a START or STOP condition.START Condition
The START Condition precedes all commands to thedevice, and is defined as a HIGH to LOW transition ofSDA when SCL is HIGH. The CAT24WC256 monitorsthe SDA and SCL lines and will not respond until thiscondition is met.STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGHdetermines the STOP condition. All operations must endwith a STOP condition.
many as four devices on the same bus. These bits mustcompare to their hardwired input pins. The last bit of theslave address specifies whether a Read or Write opera-tion is to be performed. When this bit is set to 1, a Readoperation is selected, and when set to 0, a Write opera-tion is selected.
After the Master sends a START condition and the slaveaddress byte, the CAT24WC256 monitors the bus andresponds with an acknowledge (on the SDA line) whenits address matches the transmitted slave address. TheCAT24WC256 then performs a Read or Write operationdepending on the state of the R/W bit.Acknowledge
After a successful data transfer, each receiving device isrequired to generate an acknowledge. The Acknowledg-ing device pulls down the SDA line during the ninth clockcycle, signaling that it received the 8 bits of data.The CAT24WC256 responds with an acknowledge afterreceiving a START condition and its slave address. If thedevice has been selected along with a write operation,it responds with an acknowledge after receiving each 8-bit byte.
When the CAT24WC256 begins a READ mode it trans-mits 8 bits of data, releases the SDA line, and monitorsthe line for an acknowledge. Once it receives this ac-knowledge, the CAT24WC256 will continue to transmitdata. If no acknowledge is sent by the Master, the device
DEVICE ADDRESSING
The bus Master begins a transmission by sending aSTART condition. The Master sends the address of theparticular slave device it is requesting. The five mostsignificant bits of the 8-bit slave address are fixed as10100(Fig. 5). The CAT24WC256 uses the next two bitsas address bits. The address bits A1 and A0 allow asFigure 4. Acknowledge Timing
SCL FROMMASTER189DATA OUTPUTFROM TRANSMITTERDATA OUTPUTFROM RECEIVERSTARTACKNOWLEDGE5020 FHD F06
Figure 5. Slave Address Bits
10100A1A0R/W5027 FHD F07
5
Doc. No. 25061-00 6/99 S-1
元器件交易网www.cecb2b.com
CAT24WC256
terminates data transmission and waits for a STOPcondition.
Preliminary
If the Master transmits more than 64 bytes before sendingthe STOP condition, the address counter ‘wraps around’,and previously transmitted data will be overwritten.When all 64 bytes are received, and the STOP conditionhas been sent by the Master, the internal programmingcycle begins. At this point, all received data is written tothe CAT24WC256 in a single write cycle.Acknowledge Polling
Disabling of the inputs can be used to take advantage ofthe typical write cycle time. Once the stop condition isissued to indicate the end of the host's write operation,CAT24WC256 initiates the internal write cycle. ACKpolling can be initiated immediately. This involves issu-ing the start condition followed by the slave address fora write operation. If CAT24WC256 is still busy with thewrite operation, no ACK will be returned. IfCAT24WC256 has completed the write operation, anACK will be returned and the host can then proceed withthe next read or write operation.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends theSTART condition and the slave address information(with the R/W bit set to zero) to the Slave device. Afterthe Slave generates an acknowledge, the Master sendstwo 8-bit address words that are to be written into theaddress pointers of the CAT24WC256. After receivinganother acknowledge from the Slave, the Master devicetransmits the data to be written into the addressedmemory location. The CAT24WC256 acknowledgesonce more and the Master generates the STOP condi-tion. At this time, the device begins an internal program-ming cycle to nonvolatile memory. While the cycle is inprogress, the device will not respond to any request fromthe Master device.Page Write
The CAT24WC256 writes up to 64 bytes of data, in asingle write cycle, using the Page Write operation. Thepage write operation is initiated in the same manner asthe byte write operation, however instead of terminatingafter the initial byte is transmitted, the Master is allowedto send up to 63 additional bytes. After each byte hasbeen transmitted, CAT24WC256 will respond with anacknowledge, and internally increment the six low orderaddress bits by one. The high order bits remain un-changed.
Figure 6. Byte Write Timing
STARTSACKWRITE PROTECTION
The Write Protection feature allows the user to protectagainst inadvertent programming of the memory array.If the WP pin is tied to VCC, the entire memory array isprotected and becomes read only. The CAT24WC256will accept both slave and byte addresses, but thememory location accessed is protected from program-ming by the device’s failure to send an acknowledgeafter the first byte of data is received.
BUS ACTIVITY:MASTERSDA LINESLAVEADDRESSBYTE ADDRESSA15–A8A7–A0DATASTOPP*ACKACKACK24WC256 F08
*=Don't Care Bit
Figure 7. Page Write Timing
STARTSACKBUS ACTIVITY:MASTERSDA LINESLAVEADDRESSBYTE ADDRESSA15–A8A7–A0DATADATA nDATA n+63STOPP*ACKACKACKACKACKACK24WC256F09
*=Don't Care Bit
Doc. No. 25061-00 6/99 S-1
6
元器件交易网www.cecb2b.com
Preliminary
CAT24WC256
wishes to read. After CAT24WC256 acknowledges, theMaster device sends the START condition and the slaveaddress again, this time with the R/W bit set to one. TheCAT24WC256 then responds with its acknowledge andsends the 8-bit byte requested. The master device doesnot send an acknowledge but will generate a STOPcondition.Sequential Read
The Sequential READ operation can be initiated byeither the Immediate Address READ or Selective READoperations. After the CAT24WC256 sends the initial 8-bit byte requested, the Master will respond with anacknowledge which tells the device it requires moredata. The CAT24WC256 will continue to output an 8-bitbyte for each acknowledge sent by the Master. Theoperation will terminate when the Master fails to respondwith an acknowledge, thus sending the STOP condition.The data being transmitted from CAT24WC256 is out-putted sequentially with data from address N followed bydata from address N+1. The READ operation addresscounter increments all of the CAT24WC256 address bitsso that the entire memory array can be read during oneoperation. If more than E (where E=32767) bytes areread out, the counter will ‘wrap around’ and continue toclock out data bytes.
READ OPERATIONS
The READ operation for the CAT24WC256 is initiated inthe same manner as the write operation with one excep-tion, that R/W bit is set to one. Three different READoperations are possible: Immediate/Current AddressREAD, Selective/Random READ and Sequential READ.Immediate/Current Address Read
The CAT24WC256’s address counter contains the ad-dress of the last byte accessed, incremented by one. Inother words, if the last READ or WRITE access was toaddress N, the READ immediately following would ac-cess data from address N+1. If N=E (where E=32767),then the counter will ‘wrap around’ to address 0 andcontinue to clock out data. After the CAT24WC256receives its slave address information (with the R/W bitset to one), it issues an acknowledge, then transmits the8 bit byte requested. The master device does not sendan acknowledge, but will generate a STOP condition.Selective/Random Read
Selective/Random READ operations allow the Masterdevice to select at random any memory location for aREAD operation. The Master device first performs a‘dummy’ write operation by sending the START condi-tion, slave address and byte addresses of the location it
Figure 8. Immediate Address Read Timing
BUS ACTIVITY:MASTERSDA LINESTARTSSLAVEADDRESSDATASTOPPACKNOACKSCL89SDA8TH BITDATA OUTNO ACKSTOP24WC128 F107
24WC256 F10
Doc. No. 25061-00 6/99 S-1
元器件交易网www.cecb2b.com
CAT24WC256
Figure 9. Selective Read Timing
STARTSACKSTARTSACKACKACKNOACKPreliminary
BUS ACTIVITY:MASTERSDA LINESLAVEADDRESSBYTE ADDRESSA15–A8A7–A0SLAVEADDRESSDATASTOPP**=Don't Care Bit
24WC256 FIG. 11
24WC128 F11Figure 10. Sequential Read TimingBUS ACTIVITY:MASTERSDA LINEACKACKACKACKNOACK5020 FHD F12
SLAVEADDRESSDATA nDATA n+1DATA n+2DATA n+xSTOPPORDERING INFORMATION
PrefixCATDevice #24WC256KSuffixI-1.8TE13OptionalCompany IDProductNumberTemperature RangeBlank = Commercial (0˚ - 70˚C)I = Industrial (-40˚ - 85˚C)A = Automotive (-40˚ - 105˚C)*Tape & ReelTE13: 2000/ReelPackageP: PDIPK: SOIC (EIAJ)Operating VoltageBlank: 2.5 to 6.0V1.8: 1.8 to 6.0V3: 3.0V to 5.5V* -40˚ to +125˚C is available upon request24WC256 FIG. 13Notes:
(1) The device used in the above example is a 24WC256KI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating
Voltage, Tape & Reel)
Doc. No. 25061-00 6/99 S-1
8
因篇幅问题不能全部显示，请点此查看更多更全内容