BY James Yeh and Hunter Ho
Abstract
Synchronous rectifier buck operation in high switch frequency will generate the spike voltage and ringing due to the stray inductance and capacitance exist in practical PCB. In this paper will discuss the source of the spike voltage in detail and how to select and design suitable snubber circuit to decrease it. Theoretical analysis, simulation and experimental result could provide some information, for related engineer.
1.Introduction
Synchronous rectifier buck is widely used in the power supply of many electronic
equipment, due to it has fast response, simple topology, higher efficiency for a low voltage and high current need. But it still has a serious problem “EMI”. While the switch turn on and turn off in a high frequency, the stray inductance and capacitance exist in practical PCB, it will generate high frequency ringing and spike voltage. The high frequency ringing and spike voltage will interference the equipment or damage the switch. In order to solve this problem, there are some methods such as “soft switching”, “snubber circuit”, and ”add EMI filter”. In this paper, we will discuss what cause spike and ringing in detail, and how to place a simple passive component (snubber circuit) to solve this drawback.
2.Sourse analysis of spike voltage and how to suppress
Figure 1 shows a typical synchronous rectifier Buck converter, where Ls1 and Ls2 are the stray inductance due to the finite size of the circuit layout. In practical circuits operation, while the Vg2 signal has been low and Vg1 has not reach high yet, it is called the dead time. The load current flows through the body diode D2 and stray inductance Ls2. During the dead time, item the Vg1 has been already high, then the M1 has been turned on and D2 start to add reverse voltage. But the body diode with reverse voltage exist a reverse recovery current (Irr), it practical turn off has to across a reverse recovery time (trr) and has the snap-off current during the extremely short time ts. The snap-off body diode current as show in Figure 2 can produce the transient high peak voltage, and ringing. It may be generate EMI to inference the controller or others equipment and the high peak voltage may be to damage the MOSFET (M2). For different position of stray inductance, a high frequency capacitor (Cd) and RC Snubber circuit must be placed across the drain of M1 to ground and lower switch (M2) of the synchronous rectifier buck converter, respectively, to reduce the peak voltage and to damp the ringing. The circuit as shows in Figure 3.
Although the spike and the ringing are due to snap-off current of body diode (D2), according
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to the different position of stray inductance, we can provide the different solution. Find a proper capacitance (Cd) is enough to decrease the spike and ringing, if there is only Ls1 in circuit. But if the Ls2 is existence simultaneously, the snubber circuit (Rs-Cs) must be placed across the low-side MOSFET (M2) to protect the Mosfet and damp the ringing. It will be discussed in the different situation and solved as below:
D1Ls112M1Ls2Vg1VdCinM2Vg2D21RLCL2Vphase1L120
Figure 1. Typical Synchronous Rectifier Buck converter
M1 OFFM1 ONiD2
tst
IrrtrrD1Ls112M1Ls2Vg1VdCinCdM2Vg2t0Figure 2. Body diode current
L112
Vphase21RsD2CsRLCL0
Figure 3. Synchronous Rectifier Buck converter with high frequency
input capacitor and R-C snubber circuit
2
Case 1:
First, assume the stray inductance Ls2»0, at the instant of body diode reverse-recovery current snap off, the equivalent circuit as shows in Figure 4, Cp is the stray capacitance includes the junction capacitance of the switch and stray capacitance due to circuit layout and mounting. For analyzing this equivalent circuit the instant of diode snap-off is treated as t=0. The initial inductor current is Irr as showed in Figuere2 and initial capacitor voltage is
Irr
+Vd, it is a large value of spike zero. While the body diode snap-off the Vphase=Ls1ts
voltage at the instant, and the Ls1 and Cp will generate high frequency ringing. The
1
, it is damped by only equivalent- series -resister oscillated frequency is wo=
Ls1Cp(ESR). In this case, we could place the high frequency capacitor (Cd), and enough to decrease the spike and ringing. Figure 5 shows the equivalent circuit of converter with the high frequency input capacitance, and the initial capacitance voltage of Cd is Vd, so Cd
It
must has capability to provide Qrr. The Qrr=rrrr, and
2
Q
Cd>10rr: (1)
Vd
Ls1
+Vd-t=0Cp
Vphase
Figure 4. Body diode snap-off equivalent circuit
Ls1
+Vd-Cdt=0VphaseCp
Figure 5. Body diode snap-off equivalent circuit with high frequency input capacitor.
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In the component selection of Cd, at least one low ESR capacitor should be used to provide good performance. Here, to adopt either the ceramic or the tantalum type is suitable, and it should be as close to M1 (up-side Mosfet) as possible when layout.
Example 1. Consider Figure 3.circuit, assume Io=10A, Ls1=1nH, Ls2=0, Vd=12V, Vo=5V,
L1=10mH, Cin=CL=1000mF, fs=100kHz, body diode trr=19nS, Irr=78A Figure 6 shows the wave of Vphase that is simulated by Pspice. While the
body diode reverse recovery, the Vphase has a 30 V spike voltage.
100A
0A
SEL>>-100A
(IS(M3)+IB(M3))30VIrr
Vphase20V10V0V8.0199187ms8.0199500msV(R2:2)
8.0200000ms8.0200500ms Time
8.0201000ms8.0201500ms
Figure 6.The wave of Vphase that is simulated by Pspice. While the body diode snap-off
In order to reduce spike, we add a capacitor Cd. According equation (1), Cd=0.1mF. The simulated result is shown in Figure 7. Figure 8 shows the simulated result which the
Cd=1mF, According to simulated result, we can see a greater value of Cd with a better capability to reduce spike voltage. Here, the Cd is also an EMI filter.
100A
0A
SEL>>-100A
Irr(IS(M3)+IB(M3))
30V
Vphase20V
10V
0V
8.01992ms
V(R2:2)
8.01996ms
8.02000ms
8.02004ms Time
8.02008ms
8.02012ms
8.02016ms
Figure 7. The simulated result which Cd=0.1m..
4
100A
0A
-100A
(IS(M3)+IB(M3))30V
Irr
20V
Vphase10V
SEL>>-2V
8.01992ms
V(R2:2)
8.01996ms8.02000ms8.02004ms Time
8.02008ms8.02012ms8.02016ms
Figure 8. The simulated result which the Cd=1m
Case 2:
Assume Ls1»0, the equivalent circuit is the same as Figure 4. But in this case should be added a snubber circuit to decrease the spike voltage across M2, the equivalent circuit is shown in Figure 6.
Ls2+VdCathodeRs
-AnodeCs
Figure 9. Body diode snap-off equivalent circuit with R-C snubber
In this two-order transient circuit, the initial inductor current is Irr and the initial capacitor voltage is zero, at t=0. The differential equation of the body diode voltage and the boundary condition are as showed below:
Ls2Cs
d2Vdf(t)dt
+RsCs
dVdf(t)dt
+Vdf(t)=-Vd (2)
Vdf(0+)=-IrrRs (3)
5
dVdf(0+)dt
IrrRsVdIrrRs2=--- (4)
CsLs2Ls2
The solution of equation (2) is
Vdf(t)=-Vd-Ls2Irr
e-atcos(wat-f-g) (5)
Cscos(j)
where
RV-IrrRs/2wa2
wa=1-2 , a=s , f=tan-1(\"d), and g=tan-1(a) (6)
2w0waLs2Irraw0
In equation (5), the maximum voltage across body diode can be found by setting the derivative dVdf(t)/dt=0, and we can get tm which is the maximum voltage time.
j+g-p2tm=³0 (7)
wa
To substitute t=tm into equation (4) and define Cbase=Ls2(Irr/Vd)2, Rbase=Vd/Irr we can get the maximum reverse voltage which across the low side Mosfets M2 as shown in equation (8).
VmaxCRR
=1+[1+base+s-0.75(s)3]e-atm (8) VdCsRbaseRbase
From equation (8), we can detect the oscillations are damped out by Rs and the maximum
voltage is depended on the values of Rs and Cs.
The energy loss in the resistor is
112
WR=Ls2Irr+CsVd2 (9)
22
The energy stored in Cs is equal to
6
WC=CsVd2 (10)
The total energy dissipation is
Wtot=WR+WCs=
12Ls2Irr+CsVd2 (11) 2
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The above design equation is too complex. In most cases a simple design technique is need to determine suitable values for the snubber components (Rs and Cs). Here, we introduce a simple method. First select a snubber capacitor with a value that is 4-10 times larger than the estimated capacitance of the synchronous switch (M2) and which mounting
V
capacitance. Rs is selected so that Rs=d. This means that the initial voltage step due to
Io
the current flowing in Rs is no greater than the clamped input voltage. The dissipated power in Rs can be estimated from peak energy stored in Cs:
Pdiss»CsVd2fs (12)
where
fs is the switch frequency.
Example 2. To consider the same conditions of example 1, the difference is Ls1=0 and
Ls2=0.5nH. Figure 10 shows the body diode reverse recovery current and voltage across the synchronous switch (M2), it exist a 35 V spike voltage.
50A
0A
-50A
SEL>>-94A
(IS(M3)+IB(M3))
30
20
10
0
8.0699694ms8.0699800ms
V(L2:1)
8.0700000ms
8.0700200ms
Time
8.0700400ms
8.0700600ms
8.0700800ms
Figure 10.The body diode reverse recovery current and voltage across the
synchronous switch (M2), in Ls2=0.5nH
In order to decrease this spike voltage, we can add the Rs=1 Ω, and Cs=0.1mF .The result of simulation is shown in Figure 11.The spike voltage has been suppressed to 23V,and the ringing has been reduced, too. AS the amount of Cs increase , the spike voltage will reduce
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further. However, the total energy dissipation increases linearly with Cs.
100A
0A
Irr-100A
(IS(M3)+IB(M3))30V
Vphase20V
10V
SEL>>-2V
8.0599616ms8.0599800ms
V(L2:2)
8.0600000ms8.0600200ms8.0600400ms
Time
8.0600600ms8.0600800ms8.0601000ms8.0601200ms
Figure 11. The result of simulation which is added the
snubber circuit (Rs=1 Ω, and Cs=0.1mF ).
Case 3:
Assume Ls1 and Ls2 are exist simultaneously, as shows in Figure3. Adding Cd to decrease the ringing and noise of Vphase and filter high frequency noise, moreover adding the snubber circuit (Rs-Cs) will suppress the spike voltage across the synchronous switch (M2).
Sometimes we need to sense the Vphase signal, then the serious ringing and spike voltage will influence normal operation of the control IC. Adding a high frequency capacitor Cd, will not able to reduce the ringing that is due to stray inductance Ls2. In this case, adding a suitable snubber circuit can get a better performance.
3.Experimental Results
The following a practical design example is for further understand the snubber.
The experimental circuit is shown in Figure3.The parameters are Vd=5V, Vo=2.5V, Io=5A, L1=7.8mH, Cin= 3000mF, CL =1680mF, M1and M2 are Philips’s 66NQ03LT, and control IC is RT9202 which is made by RichTek. We are measured the stray inductances Ls1= 0.1nH, Ls2=0.2nH. For how to measure the stray inductance, we provide a simple method. At first, measure the drain to source voltage ringing cycle (T1) of the synchronous switch (M2), then to add a known capacitor Ctest in parallel with the switch and finally re-measuring the period (T2). The Ls1+Ls2 can be get from:
1
) (13) Lst=Ls1+Ls2=(T22-T12)(
4pCtest
Usually Ctest is approximately equal to twice the switch capacitance. Next, adding a large Cd to decouple the influence of Ls1, and follow the above method to measure again to get the Ls2, then Ls1=Lst-Ls2.
Figure 12 shows a practical measured wave of the Vphase and the voltage across the
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synchronous rectifier switch (M2) without any snubber circuit. According to Figure 12 we can tell the ringing is very serious, and the efficiency of converter is 89%. Figure 13 shows the wave which only adding Cd=3mF, the ringing will not improve further due to the Ls2 existence. For reduce the ringing in Vphase, consider adding snubber circuit (Rs=1Ω, Cs=0.01mF). Figure 14 shows the wave which circuit have been added the snubber without adding Cd. Then observation, the ringing and spike voltage have been reduced, and in this condition the efficiency of converter is also 88%. Figure 15 shows the same wave which Cd=3mF, and the snubber circuit (Rs=1Ω, Cs=0.01mF), its efficiency is 88%. We find the ringing and spike voltage have been reduced. Figure16, 17,18 and 19 shows the same wave, the difference is load current Io=20A.
Vphase
VDS2
IDS2
Figure 12 The wave of Vphase and the voltage across the synchronous
rectifier switch (M2) without snubber.
(CH1:2A/div, Ch2: 10V/div, Ch3:1V/div,t:40ns/div)
VPHASE
VDS2
IDS2
Figure 13. The wave of Vphase and the voltage across the synchronous
rectifier switch (M2) which is added .Cd=3mF
9
(CH1:2A/div, Ch2: 10V/div, Ch3:1V/div,t:40ns/div)
VPHASE
VDS2
IDS2
Figure 14. The wave of Vphase and the voltage across the synchronous
rectifier switch (M2) which is added snubber circuit
(Rs=1Ω, Cs=0.01mF)
(CH1:2A/div, Ch2: 10V/div, Ch3:1V/div,t:40ns/div)
Vphase
VDS2
IDS2
Figure 15.The wave of Vphase and the voltage across the synchronous
rectifier switch (M2) which is added snubber circuit
(Rs=1Ω, Cs=0.01mF) and Cd=3mF
(CH1:2A/div, Ch2: 10V/div, Ch3:1V/div,t:40ns/div)
10
Vphase
VDS2
IDS2
rectifier switch (M2) without snubber. When Io=20A (CH1:2A/div, Ch2: 2V/div, Ch3:1V/div,t:80ns/div)
Figure.16 The wave of Vphase and the voltage across the synchronous
Vphase
VDS2
IDS2
F17 The wave of Vphase and the voltage across the synchronous rectifier switch (M2) which is added .Cd=3mF When Io=20A
(CH1:2A/div, Ch2: 2V/div, Ch3:1V/div,t:80ns/div)
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Vphase
VDS2
IDS2
F18 The wave of Vphase and the voltage across the synchronous
rectifier switch (M2) which is added snubber circuit
(Rs=1Ω, Cs=0.01mF) When Io=20A
(CH1:2A/div, Ch2: 2V/div, Ch3:1V/div,t:80ns/div)
Vphase
VDS2
IDS2
F19 The wave of Vphase and the voltage across the synchronous
rectifier switch (M2) which is added snubber circuit
(Rs=1Ω, Cs=0.01mF) and Cd=3mF When Io=20A (CH1:2A/div, Ch2: 2V/div, Ch3:1V/div,t:80ns/div)
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For efficiency consideration, adding snubber circuit cannot improve the total energy loss of converter further. Because the energy loss due to the reverse recovery current of body diode has been transmit to snubber resistance (Rs). But it is really effective to restrict the voltage spike. In this way, we can reduce power device rating, and improve the EMI, output noise.
4.Conclusion
One of the primary reasons for using snubbers is the presence of the stray inductance in the circuit that generate voltage spikes and ringing when excited by the switching action and diode turn off. Larger stray inductance means larger snubber components and more dissipation. As power levels rise, this becomes progressively more important because of the increasing di/dt. So before actually designing the snubber, it is important to minimize the circuit stray inductance and take good care of circuit layout.
Reference
[1] William McMurray, “ Optimum Snubbers for Power Semiconductors”, IEEE IAS
Transactions, Vol. IA-8, No,5, Sep/Oct 1972,pp. 593-600.
[2] Jim Hagerman and Hagerman Technology, “Calculating Optimum Snubbers”.
[3] Rudy Severns ”Design of Snubbers for Power Circuit”.
[4] Mohan, Undeland, and Robbins, “ Power electronics Converters, Applications, and
Design”.
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