2 Kbit serial presence detect (SPD) EEPROM
for double data rate (DDR1 and DDR2) DRAM modules
Features
■■■■■■■■
2 Kbit EEPROM for DDR1 and DDR2 serial presence detect
Backward compatible with the M34C02Permanent and reversible software data protection for lower 128 bytes
100kHz and 400kHz I2C bus serial interfaceSingle supply voltage:–1.7 V to 5.5 V
Byte and Page Write (up to 16 bytes)Self-timed write cycle
Noise filtering
–Schmitt trigger on bus inputs–Noise filter on bus inputsEnhanced ESD/latch-up protectionMore than 1 million erase/write cyclesMore than 40 years’ data retentionECOPACK® (RoHS compliant) packagesPackages:
– ECOPACK2® (RoHS-compliant and Halogen-free)
UFDFPN8 (MB or MC)2 x 3 mm■■■■■
TSSOP8 (DW)4.4 × 3 mmMay 2011Doc ID 10367 Rev 111/34
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ContentsM34E02, M34E02-F
Contents
12
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.12.22.32.42.5
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5.12.5.22.5.32.5.4
Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.13.23.33.43.53.6
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Setting the write-protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.6.13.6.2
SWP and CWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13PSWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.7Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7.13.7.23.7.3
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . 16
3.8Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.8.13.8.23.8.33.8.4
Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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M34E02, M34E02-FContents
5Use within a DDR1/DDR2 DRAM module . . . . . . . . . . . . . . . . . . . . . . . 18
5.1
Programming the M34E02 and M34E02-F . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.15.1.2
Isolated DRAM module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18DRAM module inserted in the application motherboard . . . . . . . . . . . . 19
678910
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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List of tablesM34E02, M34E02-F
List of tables
Table 1.Table 2.Table 3.Table 4.Table 5.Table 6.Table 7.Table 8.Table 9.Table 10.Table 11.Table 12.Table 13.Table 14.Table 15.Table 16.Table 17.Table 18.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12DRAM DIMM connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Acknowledge when writing data or defining the write-protection
(instructions with R/W bit = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Acknowledge when reading the write protection (instructions with R/W bit = 1). . . . . . . . . 20Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Operating conditions (for temperature range 1 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . 23Operating conditions (for temperature range 6 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . 23AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24DC characteristics (for temperature range 1 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24DC characteristics (for temperature range 6 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 30Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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M34E02, M34E02-FList of figures
List of figures
Figure 1.Figure 2.Figure 3.Figure 4.Figure 5.Figure 6.Figure 7.Figure 8.Figure 9.Figure 10.Figure 11.Figure 12.Figure 13.Figure 14.Figure 15.
Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6TSSOP and MLP connections (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Maximum RP value versus bus parasitic capacitance (C) for an I2C bus. . . . . . . . . . . . . . . 9I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Result of setting the write protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Setting the write protection (WC = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Write mode sequences in a non write-protected area . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Write cycle polling flowchart using ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Read mode sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Serial presence detect block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21AC measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 30
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DescriptionM34E02, M34E02-F
1 Description
The M34E02 and M34E02-F are 2 Kbit serial EEPROM memories able to lock permanently the data in its first half (from location 00h to 7Fh). This facility has been designed specifically for use in DRAM DIMMs (dual interline memory modules) with serial presence detect (SPD). All the information concerning the DDR1 or DDR2 configuration of the DRAM module (such as its access speed, size and organization) can be kept write-protected in the first half of the memory.
The first half of the memory area can be write-protected using two different software write protection mechanisms. By sending the device a specific sequence, the first 128 bytes of the memory become write protected: permanently or resettable. In addition, the devices allow the entire memory area to be write protected, using the WC input (for example by tieing this input to VCC).
These I2C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 256 × 8 bits.
I2C uses a two wire serial interface, comprising a bi-directional data line and a clock line. The devices carry a built-in 4-bit device type identifier code (1010) in accordance with the I2C bus definition to access the memory area and a second device type identifier code
(0110) to define the protection. These codes are used together with the voltage level applied on the three chip enable inputs (E2, E1, E0).
The devices behave as a slave device in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start
condition, generated by the bus master. The Start condition is followed by a device select code and RW bit (as described in the Device select code table), terminated by an acknowledge bit.
When writing data to the memory, the memory inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for WRITE, and after a NoAck for READ.Figure 1.Logic diagram6##%%3#,7#-%-%&3$!633!)B6/34Doc ID 10367 Rev 11
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M34E02, M34E02-F
Figure 2.TSSOP and MLP connections (top view)-%-%&%%%6336##7#3#,3$!!)BDescription
1.See the Package mechanical data section for package dimensions, and how to identify pin-1.
Table 1.
Signal names
Signal names
Description
Chip EnableSerial DataSerial ClockWrite ControlSupply voltageGround
E0, E1, E2SDASCLWCVCCVSS
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Signal descriptionM34E02, M34E02-F
2 Signal description
2.1
Serial Clock (SCL)
This input signal is used to strobe all data in and out of the device. In applications where this
signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor can be connected from Serial Clock (SCL) to VCC. (Figure4 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output.
2.2 Serial Data (SDA)
This bidirectional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure4 indicates how the value of the pull-up resistor can be calculated).
2.3 Chip Enable (E0, E1, E2)
These input signals are used to set the value that is to be looked for on the three least
significant bits (b3, b2, b1) of the 7-bit device select code. In the end application, E0, E1 and E2 must be directly (not through a pull-up or pull-down resistor) connected to VCC or VSS to establish the device select code. When these inputs are not connected, an internal pull-down circuitry makes (E0,E1,E2) = (0,0,0).
The E0 input is used to detect the VHV voltage, when decoding an SWP or CWP instruction.Figure 3.Device select code6##6##-%-%&%I-%-%&%I633633!IB2.4 Write Control (WC)This input signal is provided for protecting the contents of the whole memory from
inadvertent write operations. Write Control (WC) is used to enable (when driven low) or disable (when driven high) write instructions to the entire memory area or to the Protection Register.
When Write Control (WC) is tied low or left unconnected, the write protection of the first half of the memory is determined by the status of the Protection Register.
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M34E02, M34E02-FSignal description
2.5
2.5.1
Supply voltage (VCC)
Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table8). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10nF to 100nF) close to the VCC/VSS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW).
2.5.2 Power-up conditions
The VCC voltage has to rise continuously from 0V up to the minimum VCC operating voltage
defined in Table8 and the rise time must not vary faster than 1V/µs.
2.5.3 Device reset
In order to prevent inadvertent write operations during power-up, a power-on reset (POR)
circuit is included. At power-up, the device does not respond to any instruction until VCC reaches the internal reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Table8).
When VCC passes over the POR threshold, the device is reset and enters the Standby Power mode. However, the device must not be accessed until VCC reaches a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range.
In a similar way, during power-down (continuous decrease in VCC), as soon as VCC drops below the power-on reset threshold voltage, the device stops responding to any instruction sent to it.
2.5.4 Power-down conditions
During power-down (continuous decrease in VCC), the device must be in Standby Power
mode (mode reached after decoding a Stop condition, assuming that there is no internal write cycle in progress).Figure 4.Bus line pull-up resistor (k)100When tLOW = 1.3 µs (min value forfC = 400 kHz), the Rbus × Cbustime constant must be below the 400 ns time constant linerepresented on the left. Cbus = 400 nsMaximum RP value versus bus parasitic capacitance (C) for an I2C busVCC104 kΩRbus ×Here Rbus × Cbus = 120 nsRbusI²C busmasterSCLSDAM24xxx11030 pF100Bus line capacitor (pF)1000Cbusai14796bDoc ID 10367 Rev 119/34
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Signal description
Figure 5.I2C bus protocolM34E02, M34E02-F
SCLSDASDAInputSDAChangeStartconditionStopconditionSCL123789SDAMSBACKStart conditionSCL123789SDAMSBACKStopconditionAI00792cTable 2.
Device select code
Chip Enable signals
Device type identifierb7(1)1
b60
b51
b40
Chip Enable bitsb3E200
0
1
1
0
E200E2
b2E101E101E1
b1E011E011E0
RWb0RW000111
Memory area select code (two arrays)(2)Set write protection (SWP)
Clear write protection (CWP)
Permanently set write protection (PSWP)(2)Read SWPRead CWPRead PSWP(2)
E2VSSVSSE2VSSVSSE2
E1E0
VSSVHV(3)VCCVHV(3)E1
E0
VSSVHV(3)VCCVHV(3)E1
E0
1.The most significant bit, b7, is sent first.
2.E0, E1 and E2 are compared against the respective external pins on the memory device.3.VHV is defined in Table13.
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分销商库存信息:
STM
M34E02-FDW1TPM34E02-FDW6TP
M34E02-FMB1TG
M34E02-FMC6TG
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