基于MIPS指令的单周期微控制器设计哈工大

2023-05-04 来源：乌哈旅游

课程设计说明书（论文）

课程名称：数字集成系统课程设计设计题目：基于MIPS指令的单周期微控制器设计院系：航天学院微电子科学与技术系班级：设计者：学号：指导教师：设计时间： 2015年7月27日-2015年8月7日

姓名：院（系）：专业：班号：任务起至日期： 2015 年 7 月 27 日至 2015 年 8 月 7 日课程设计题目：基于MIPS指令的单周期微控制器设计已知技术参数和设计要求： Load/store，算术逻辑运算和流程控制是RISC的主要组成部分，本设计以MIPS指令子集为例，研究RISC的基本原理与硬件建模。（1） load/store设计设计要求：参考《计算机组成与设计—硬件/软件接口》，进行模块划分和设计微控制器整体结构，设计支持load、store指令的数据通路，并比较各种实现的效率、面积和速度。（2）算术逻辑运算设计设计要求：设计支持add、sub、multi、or等指令的数据通路。（3）流程控制设计设计要求：设计支持branch、jump等指令的数据通路。（4）基于MIPS指令的单周期微控制器设计设计要求：同组同学共同完成具有10条左右指令的单周期微控制器设计。基本要求： 1）确定设计采用的结构 2）划分所确定的结构，画出模块图，确定模块间的连接关系，端口方向及宽度 3）确定设计的验证方案，验证点及验证向量 4）完成设计的RTL建模及测试平台建模 5）完成设计的验证、逻辑综合，给出设计的评价（面积、速度） 6）完成设计报告工作量：本课程设计按照每4人一组分工协作完成。每位成员完成设计要求中的（1）～（3）任务之一，作为独立完成项，在完成个人项目基础上共同完成设计要求中的第（4）项。熟悉开发环境、学习EDA工具使用：10学时分析题目、确定设计方案：5学时设计、验证、综合以及结果分析、整理数据：25学时工作计划安排： 2015.7.27—2015.7.28 学习modelsim、DesignCompiler使用方法 2015.7.29—2015.7.30 分析设计题目，确定结构及模块划分 2015.7.31—2015.8.6 完成设计、验证、综合与性能分析 2015.8.7 提交课程设计报告同组设计者及分工：指导教师签字___________________ 年月日教研室主任意见：教研室主任签字___________________ 年月日 *注：此任务书由课程设计指导教师填写。

一、功能描述

基于MIPS指令的单周期微控制器设计：

l_w和s_w指令的实现：控制器实现支持load word(lw)、store word(sw)指令的MIPS单周期数据通路：

l_w：寄存器rs中的数据和立即数imm相加，得到存储器地址，用这个地址访问存储器，把得到的存储器数据写入寄存器rt中。把PC + 4写入PC。

s_w：寄存器rs中的数据和立即数imm相加，得到存储器地址，把寄存器rt中的数据写入这个地址的存储器中。把PC + 4写入PC。

二、设计方案： 1. 整体框图：

2. 模块划分：

下图中，各个大模块中还包含：立即数符号位扩展，寄存器堆，存储器，ALU，指令寄存器，PC，控制部件

3. 模块连接框图：

4. 总体设计思想：

我设计的部分主要包三四部分，分别为：指令寄存器、寄存器堆、和存储器，额外还有一个Alu，即加法器和一个pc，即程序计数器，是借助同组同学编译的程序。

存取指令需要两个状态单元，计算下一个指令地址需要一个加法器，两个状态单元分别是指令寄

存器和程序寄存器。指令寄存器是制度的，任意时刻的输出都反映了输入的地址的内容，而不需要读控制信号。程序计数器是一个32位的寄存器，让在每个时钟周期末都会被写入。加法器被设计为只进行加法运算的ALU，他将输入的俩个32位数相加将结果输出。

Mips指令执行时，首先需要的是指令存储器，用来存储指令，并根据所给地址提供指令，指令地址存放在pc中，pc的设计还需要一个加法器来指向下一个指令的地址。在执行R型指令时，读两个寄存器，对他们中的内容进行Alu操作，再写出结果。

处理器的32个寄存器组成一个寄存器堆的结构，即register。

在读取指令的时候，一般形式为：op rs rt imm，此时需要将一个16位的立即数带符号扩充为32位，然后和rs地址内的内容通过Alu加法器相加，如果是读取指令即load word ,即得出的是存储器地址，将得出的存储器地址内的内容写入rt所指的寄存器地址处，如果是存储指令即store word，即得出的存储器地址用来写入rt地址内的所存内容。

5. PC程序计数器：

6. L_w电路图：

7. L_w的设计思想：

sw rt, imm(rs) ; memory[rs+(sign)imm]<--rt 即 op 101011 6bits rs rs 5bits rt rt 5bits imm imm 16bits 寄存器rs中的数据和立即数imm相加，得到存储器地址，用这个地址访问存储器，把得到的存储器数据写入寄存器rt中。

8. S_w电路图：

9. S_w的设计思想：

Op 100011 6bits rs rs 5bits rt rt 5bits imm imm 16bits 寄存器rs中的数据和立即数imm相加，得到存储器地址，把寄存器rt中的数据写入这个地址的存储器中。

三、验证方案与结果分析： L_w和s_w的仿真验证：以下为指令寄存器中内容： register[17]=8'b0000_0001;//lw register[18]=8'b0000_0000; register[19]=8'b0010_0101; register[20]=8'b1000_1100; register[21]=8'b0000_0010;//lw register[22]=8'b0000_0000; register[23]=8'b0010_0110; register[24]=8'b1000_1100; register[25]=8'b0000_0011;//lw register[26]=8'b0000_0000; register[27]=8'b0010_0111; register[28]=8'b1000_1100;

以第一个地址指令为例：前六位1000_11为load指令，之后五位00001为rs，取出存储器中地址为1的内容，register[1]=1，后16位为立即数，将register [1]和立即数相加，此时为2，然后取出存储器地址为2处的内容，此时为register[2]=12'b101001_100000，再过4s，执行第二条指令，每过4s，执行下一条指令。

以store第一个指令为例：前六位1010_11为store指令，之后五位00001为rs，取出寄存器地址为rt中内容中地址为1的内容，register[1]=1，后16位为立即数，将register [1]和立即数相加，此时为2，然后取出存寄存器地址为2处的内容，将其存入2地址的存储器，将其再过4s，执行第二条指令，每过4s，执行下一条指令。

整体功能验证：

四、逻辑综合及性能分析：

1.Regfile寄存器堆节选：

2.立即数扩展：

3.ALU综合验证：

4.Control综合验证：

5.PC：

6.pc_next：

7.2选1：

8.整体cpu模块连接：

9.DC综合：design_vision> read_file -format verilog {/home/homeO5/user1/dbf4/alu.v /home/homeO5/user1/dbf4/control.v /home/homeO5/user1/dbf4/cpu_top.v

/home/homeO5/user1/dbf4/l_s.v /home/homeO5/user1/dbf4/pc.v /home/homeO5/user1/dbf4/regfile.v} Loading verilog files: '/home/homeO5/user1/dbf4/alu.v' '/home/homeO5/user1/dbf4/control.v' '/home/homeO5/user1/dbf4/cpu_top.v' '/home/homeO5/user1/dbf4/l_s.v' '/home/homeO5/user1/dbf4/pc.v' '/home/homeO5/user1/dbf4/regfile.v'

Detecting input file type automatically (-rtl or -netlist). Running DC verilog reader

Reading with Presto HDL Compiler (equivalent to -rtl option). Running PRESTO HDLC

Compiling source file /home/homeO5/user1/dbf4/alu.v Compiling source file /home/homeO5/user1/dbf4/control.v

Warning: /home/homeO5/user1/dbf4/alu.v:13: The statements in initial blocks are ignored. (VER-281)

Warning: /home/homeO5/user1/dbf4/control.v:7: Port aluc is implicitly typed (VER-987) Warning: /home/homeO5/user1/dbf4/control.v:8: Port pcsource is implicitly typed (VER-987)

Warning: /home/homeO5/user1/dbf4/control.v:29: the undeclared symbol 'i_lw' assumed to have the default net type, which is 'wire'. (VER-936)

Warning: /home/homeO5/user1/dbf4/control.v:30: the undeclared symbol 'i_sw' assumed to have the default net type, which is 'wire'. (VER-936) Compiling source file /home/homeO5/user1/dbf4/cpu_top.v

Warning: /home/homeO5/user1/dbf4/cpu_top.v:16: the undeclared symbol 'wmem' assumed to have the default net type, which is 'wire'. (VER-936)

Warning: /home/homeO5/user1/dbf4/cpu_top.v:23: The statements in initial blocks are ignored. (VER-281)

Compiling source file /home/homeO5/user1/dbf4/l_s.v

Warning: /home/homeO5/user1/dbf4/cpu_top.v:61: The statements in initial blocks are ignored. (VER-281)

Warning: /home/homeO5/user1/dbf4/l_s.v:11: The statements in initial blocks are ignored. (VER-281)

Compiling source file /home/homeO5/user1/dbf4/pc.v

Warning: /home/homeO5/user1/dbf4/pc.v:4: Port pcin is implicitly typed (VER-987) Warning: /home/homeO5/user1/dbf4/pc.v:5: Port pc4 is implicitly typed (VER-987)

Warning: /home/homeO5/user1/dbf4/pc.v:8: The statements in initial blocks are ignored. (VER-281)

Warning: /home/homeO5/user1/dbf4/pc.v:17: Port pc_in is implicitly typed (VER-987) Warning: /home/homeO5/user1/dbf4/pc.v:17: Port qa is implicitly typed (VER-987) Warning: /home/homeO5/user1/dbf4/pc.v:18: Port imm1 is implicitly typed (VER-987) Warning: /home/homeO5/user1/dbf4/pc.v:19: Port imm2 is implicitly typed (VER-987) Warning: /home/homeO5/user1/dbf4/pc.v:21: Port pc_out is implicitly typed (VER-987) Warning: /home/homeO5/user1/dbf4/pc.v:22: Port select is implicitly typed (VER-987) Compiling source file /home/homeO5/user1/dbf4/regfile.v

Warning: /home/homeO5/user1/dbf4/regfile.v:13: The statements in initial blocks are ignored. (VER-281)

Statistics for case statements in always block at line 13 in file '/home/homeO5/user1/dbf4/alu.v'

=============================================== | Line | full/ parallel | =============================================== | 23 | auto/auto | ===============================================

Warning: /home/homeO5/user1/dbf4/l_s.v:11: Potential simulation-synthesis mismatch if index exceeds size of array 'register'. (ELAB-349)

Warning: /home/homeO5/user1/dbf4/l_s.v:14: Potential simulation-synthesis mismatch if index exceeds size of array 'register'. (ELAB-349)

Inferred memory devices in process

in routine DataMem line 12 in file

'/home/homeO5/user1/dbf4/l_s.v'.

=========================================================================== | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | =========================================================================== | register_reg | Latch | 32 | Y | N | N | N | - | - | - | | register_reg | Latch | 32 | Y | N | N | N | - | - | - | =========================================================================== Statistics for MUX_OPs

=========================================================== | block name/line | Inputs | Outputs | # sel inputs | MB | =========================================================== | DataMem/11 | 256 | 32 | 8 | N | =========================================================== Warning: /home/homeO5/user1/dbf4/l_s.v:158: 'do[20:16]' is being read, but does not appear in the sensitivity list of the block. (ELAB-292) Warning: /home/homeO5/user1/dbf4/l_s.v:159: 'do[15:11]' is being read, but does not appear in the sensitivity list of the block. (ELAB-292)

Statistics for case statements in always block at line 154 in file '/home/homeO5/user1/dbf4/l_s.v'

=============================================== | Line | full/ parallel | =============================================== | 157 | auto/auto | ===============================================

Warning: /home/homeO5/user1/dbf4/l_s.v:144: Potential simulation-synthesis mismatch if index exceeds size of array 'register'. (ELAB-349)

Warning: /home/homeO5/user1/dbf4/l_s.v:145: Potential simulation-synthesis mismatch if index exceeds size of array 'register'. (ELAB-349)

Warning: /home/homeO5/user1/dbf4/l_s.v:146: Potential simulation-synthesis mismatch if

index exceeds size of array 'register'. (ELAB-349)

Warning: /home/homeO5/user1/dbf4/l_s.v:147: Potential simulation-synthesis mismatch if index exceeds size of array 'register'. (ELAB-349) Statistics for MUX_OPs

Inferred memory devices in process in routine pc line 8 in file

'/home/homeO5/user1/dbf4/pc.v'.

=============================================================================== | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | =============================================================================== | pc4_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | ===============================================================================

Warning: /home/homeO5/user1/dbf4/pc.v:34: 'qa' is being read, but does not appear in the sensitivity list of the block. (ELAB-292)

Statistics for case statements in always block at line 30 in file '/home/homeO5/user1/dbf4/pc.v'

=============================================== | Line | full/ parallel | =============================================== | 31 | auto/auto | ===============================================

Warning: /home/homeO5/user1/dbf4/regfile.v:13: Potential simulation-synthesis mismatch if index exceeds size of array 'register'. (ELAB-349)

Warning: /home/homeO5/user1/dbf4/regfile.v:14: Potential simulation-synthesis mismatch if index exceeds size of array 'register'. (ELAB-349)

Warning: /home/homeO5/user1/dbf4/regfile.v:19: Potential simulation-synthesis mismatch if index exceeds size of array 'register'. (ELAB-349)

Inferred memory devices in process

in routine regfile line 16 in file

'/home/homeO5/user1/dbf4/regfile.v'.

=============================================================================== | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | =============================================================================== | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N |

| register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | =============================================================================== Statistics for MUX_OPs

=========================================================== | block name/line | Inputs | Outputs | # sel inputs | MB | =========================================================== | regfile/13 | 32 | 32 | 5 | N | | regfile/14 | 32 | 32 | 5 | N | =========================================================== Presto compilation completed successfully.

Current design is now '/home/homeO5/user1/dbf4/alu.db:alu'

Warning: Overwriting design file '/home/homeO5/user1/dbf4/DataMem.db'. (DDB-24) Warning: Overwriting design file '/home/homeO5/user1/dbf4/InstMem.db'. (DDB-24) Loaded 11 designs.

Current design is 'alu'. design_vision>

Current design is 'alu'.

10.功能综合： Report : area Design : cpu_top Version: C-2009.06

Date : Fri Aug 7 08:43:23 2015

****************************************

Library(s) Used:

typical

/export/homeO5/libs/smic18/std_cell/2005q4v1/aci/sc-x/synopsys/typical.db)

Number of ports: 1 Number of nets: 368 Number of cells: 10 Number of references: 10

Combinational area: 144196.113892 Noncombinational area: 377346.823853

Net Interconnect area: undefined (No wire load specified)

Total cell area: 521542.937745 Total area: undefined

Report : timing -path full -delay max -max_paths 1 Design : cpu_top Version: C-2009.06

Date : Fri Aug 7 08:42:50 2015

****************************************

# A fanout number of 1000 was used for high fanout net computations.

Operating Conditions: typical Library: typical Wire Load Model Mode: top

Startpoint: r1/register_reg[13][2]

(rising edge-triggered flip-flop clocked by clk) Endpoint: r1/register_reg[1][9]

(rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max

(File:

Point Incr Path ----------------------------------------------------------- clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 r1/register_reg[13][2]/CK (EDFFX1) 0.00 # 0.00 r r1/register_reg[13][2]/QN (EDFFX1) 0.31 0.31 f r1/U84/Y (OAI222XL) 0.21 0.52 r r1/U210/Y (NOR3X1) 0.08 0.60 f r1/U208/Y (OAI21XL) 0.72 1.31 r r1/qb[2] (regfile) 0.00 1.31 r s1/a[2] (Select_0) 0.00 1.31 r s1/U18/Y (AOI22X1) 0.04 1.36 f s1/U17/Y (INVX1) 0.16 1.52 r s1/outp[2] (Select_0) 0.00 1.52 r a1/i1[2] (alu) 0.00 1.52 r a1/r65/B[2] (alu_DW01_addsub_0) 0.00 1.52 r a1/r65/U4/Y (XOR2X1) 0.15 1.67 f a1/r65/U1_2/CO (ADDFX2) 0.30 1.98 f a1/r65/U1_3/CO (ADDFX2) 0.20 2.18 f a1/r65/U1_4/CO (ADDFX2) 0.20 2.38 f a1/r65/U1_5/CO (ADDFX2) 0.20 2.58 f a1/r65/U1_6/CO (ADDFX2) 0.20 2.78 f a1/r65/U1_7/CO (ADDFX2) 0.20 2.97 f a1/r65/U1_8/CO (ADDFX2) 0.20 3.17 f a1/r65/U1_9/CO (ADDFX2) 0.20 3.37 f a1/r65/U1_10/CO (ADDFX2) 0.20 3.57 f a1/r65/U1_11/CO (ADDFX2) 0.20 3.77 f a1/r65/U1_12/CO (ADDFX2) 0.20 3.97 f a1/r65/U1_13/CO (ADDFX2) 0.20 4.17 f a1/r65/U1_14/CO (ADDFX2) 0.20 4.37 f a1/r65/U1_15/CO (ADDFX2) 0.20 4.57 f a1/r65/U1_16/CO (ADDFX2) 0.20 4.77 f a1/r65/U1_17/CO (ADDFX2) 0.20 4.97 f a1/r65/U1_18/CO (ADDFX2) 0.20 5.17 f a1/r65/U1_19/CO (ADDFX2) 0.20 5.37 f a1/r65/U1_20/CO (ADDFX2) 0.20 5.57 f a1/r65/U1_21/CO (ADDFX2) 0.20 5.76 f a1/r65/U1_22/CO (ADDFX2) 0.20 5.96 f a1/r65/U1_23/CO (ADDFX2) 0.20 6.16 f a1/r65/U1_24/CO (ADDFX2) 0.20 6.36 f a1/r65/U1_25/CO (ADDFX2) 0.20 6.56 f a1/r65/U1_26/CO (ADDFX2) 0.20 6.76 f a1/r65/U1_27/CO (ADDFX2) 0.20 6.96 f a1/r65/U1_28/CO (ADDFX2) 0.20 7.16 f a1/r65/U1_29/CO (ADDFX2) 0.20 7.36 f

a1/r65/U1_30/CO (ADDFX2) 0.20 7.56 f a1/r65/U1_31/Y (XOR3X2) 0.12 7.69 f a1/r65/SUM[31] (alu_DW01_addsub_0) 0.00 7.69 f a1/U15/Y (OAI2BB1X1) 0.15 7.84 f a1/outp[31] (alu) 0.00 7.84 f d1/a[31] (DataMem) 0.00 7.84 f d1/U1475/Y (NOR3X1) 0.11 7.95 r d1/U1474/Y (NOR4BX1) 0.15 8.10 r d1/U1476/Y (NAND4X1) 0.09 8.19 f d1/U1480/Y (NOR2X1) 0.14 8.34 r d1/U1427/Y (AND2X2) 0.13 8.46 r d1/U268/Y (NAND2X1) 0.25 8.72 f d1/U959/Y (NOR2BX1) 0.11 8.83 r d1/U958/Y (INVX1) 0.06 8.89 f d1/U358/Y (INVX1) 0.27 9.15 r d1/U1481/Y (NOR2X1) 0.05 9.20 f d1/do[9] (DataMem) 0.00 9.20 f s2/b[9] (Select_1) 0.00 9.20 f s2/U14/Y (AOI22X1) 0.13 9.33 r s2/U13/Y (INVX1) 0.21 9.54 f s2/outp[9] (Select_1) 0.00 9.54 f r1/d[9] (regfile) 0.00 9.54 f r1/register_reg[1][9]/D (EDFFX1) 0.00 9.54 f data arrival time 9.54

clock clk (rise edge) 10.00 10.00 clock network delay (ideal) 0.00 10.00 r1/register_reg[1][9]/CK (EDFFX1) 0.00 10.00 r library setup time -0.44 9.56 data required time 9.56 ----------------------------------------------------------- data required time 9.56 data arrival time -9.54 ----------------------------------------------------------- slack (MET) 0.02

五、结论：

通过两周的设计和仿真验证，我们完成了对MIPS指令的单周期CPU的设计，我主要完成了l_w和s_w指令的设计和编译，由于对Verilog语言掌握的不够熟练，编写程序时遇到很多困难，经常在编写完程序时出现多个error，在同组同学的帮助下才能找到错误，这让我知道的了扎实掌握基本设计语言的重要性。在仿真和综合验证时，由于整体的需要，程序进行了多次校验和改正，一个部分的程序很容易就编写好，但是整合在一起就会出现错误，还需很多调试改正过程，团队合作显得尤为重要。

六、源代码：

module lw_swtop(clk); input clk;

wire [31:0] pc,pc_out,qa,d,qb,r,qb1,do,imm2; wire [4:0] rs,rt,rd; wire [5:0] op,func; wire [1:0] pcsource; wire [2:0] aluc; wire [15:0] imm; wire [25:0] addr;

pc p1(pc,pc_out,clk); pc_next p2(pc,pc_out);

regfile r1(rs,rt,d,rd,we,clk,qa,qb);

alu a1(r,z,qa,qb1,aluc);

control c1(z,op,func,we,aluc,pcsource,wmem,aluimm,m2reg); DataMem d1(r,qb,wmem,do);

InstMem in1(pc,op,func,rs,rt,rd,imm,addr); full_ext fff(imm,imm2);

Select s1(qb,imm2,aluimm,qb1); Select s2(r,do,m2reg,d); //initial //

$monitor($time,”aluc=%b\\n,rs=%b\\n,rt=%b\\n,rd=%b\\n,qa=%b\\n,qb=%b,r=%b\\n,wmem=%b,d=%b,we=%b,pcsource=%b,imm=%b,imm2=%b,aluimm=%b,pc=%b,pc_out=%b\\n,m2reg=%b\,d,we,pcsource,imm,imm2,aluimm,pc,pc_out,m2reg); endmodule

module stimuluslalala; reg clk;

lw_swtop test1(clk); initial begin clk=0; forever

#4 clk=~clk; end endmodule

module pc_next(pc_in,pc_nex); input [31:0]pc_in; output [31:0]pc_nex;

assign pc_nex=pc_in+4; endmodule

module Select(a,b,s,outp); input [31:0] a,b; input s;

output [31:0] outp; wire [31:0] outp;

assign outp=(s==1)? b:a; endmodule

module alu(outp,z,i0,i1,cntr);

output [31:0] outp; output z;

input [31:0] i0,i1; input [2:0] cntr; reg [31:0] outp; reg z; initial z<=0;

always@(i0 or i1 or cntr ) begin if (i0==i1) begin z<=1; //outp<=0; end

else z<=0;

case(cntr)

3'b000: outp=i0+i1; 3'b001: outp=i0-i1; 3'b010: outp=i0&i1; 3'b011: outp=i0|i1; 3'b100: outp=i0^i1; default: outp=0;

endcase end endmodule

module pc(pc4,pcin,clk); input pcin,clk;

output pc4; wire [31:0]pcin; reg [31:0]pc4; initial pc4=1;

always @(posedge clk) pc4=pcin;

endmodule

module control(z,op,func,wreg,aluc,pcsource,wmem,aluimm,m2reg);

output wreg,aluc,pcsource,wmem,aluimm,m2reg; input z;

input [5:0]op,func; reg aluimm,m2reg; reg [2:0] aluc; reg [1:0] pcsource;

wire i_add,i_sub,i_and,i_or,i_xor;

wire r_type,j_type,ibeq_type,ibne_type,lw_type,sw_type; wire r_jr,r_lw,w_sw; wire wreg; wire wmem;

assign i_add=r_type&func[5]&~func[4]&~func[3]&~func[2]&~func[1]&~func[0]; assign i_sub=r_type&func[5]&~func[4]&~func[3]&~func[2]&func[1]&~func[0]; assign i_and=r_type&func[5]&~func[4]&~func[3]&func[2]&~func[1]&~func[0]; assign i_or=r_type&func[5]&~func[4]&~func[3]&func[2]&~func[1]&func[0]; assign i_xor=r_type&func[5]&~func[4]&~func[3]&func[2]&func[1]&~func[0]; assign r_jr=r_type&~func[5]&~func[4]&func[3]&~func[2]&~func[1]&~func[0]; assign i_lw=op[5]&~op[4]&~op[3]&~op[2]&op[1]&op[0]; assign i_sw=op[5]&~op[4]&op[3]&~op[2]&op[1]&op[0]; assign wmem=i_sw;

6'b100000:aluc=3'b000; 6'b100010:aluc=3'b001; 6'b100100:aluc=3'b010; 6'b100101:aluc=3'b011; 6'b100110:aluc=3'b100; default:aluc=3'b000;

endcase end

always @(lw_type or sw_type ) begin if(lw_type|sw_type) begin aluc=0; aluimm=1; if(lw_type) m2reg=1; else

m2reg=0; end else begin

aluimm=0; m2reg=0; end end

always @(ibeq_type or z or ibne_type or j_type or r_jr ) begin

if((ibeq_type&z)|(ibne_type&~z))

pcsource=2'b01;

else if(j_type) pcsource=2'b11;

else if(r_jr)

pcsource=2'b10; else pcsource=2'b00; end

//initial

//$monitor(\"op=%b,r_jr=%b,pcsource=%b\endmodule

module regfile(rna,rnb,d,wn,we,clk,qa,qb);

input [4:0] rna,rnb,wn; input [31:0] d; input we,clk;

output [31:0] qa,qb;

reg [31:0] register [1:31]; // $1 - $31 regs initial begin register[1]=1;

assign qa = (rna==0) ? 0 : register[rna]; assign qb = (rnb==0) ? 0 : register[rnb];

always @(posedge clk )

if (we && (wn != 0)) register[wn] <= d; initial

$monitor($time,\"register[5]=%b,register[6]=%b,register[7]=%b\

endmodule

module DataMem(a,di,we,do); input [31:0] a; input [31:0] di; input we;

output [31:0] do;

reg [31:0] register [ 1 : 65536]; initial begin register[1]=1; register[3]=5; end

assign do = ( a == 0 ) ? 0 : register[a];

always @ (a or di or we) if (we && (a != 0)) register[a] <= di; //initial

//$monitor($time,\"register[2]=%b,register[3]=%b,register[4]=%b,regisiter[5]=%b\ster[4],register[5]); endmodule

/*module ControlUnit(op,wreg,aluc,wmem); input [5:0] op;

output wreg,wmem; output [2:0] aluc; reg aluc;

assign i_lw=op[5]&~op[4]&~op[3]&~op[2]&op[1]&op[0]; assign i_sw=op[5]&~op[4]&op[3]&~op[2]&op[1]&op[0]; assign wreg=i_lw; assign wmem=i_sw; initial begin

aluc=3'b000; end

endmodule;*/

module full_ext(im16,im32); input[15:0] im16; output[31:0] im32; wire[15:0] im16; reg[31:0] im32; always@(im16) begin

if(im16[15]==1) im32=(im16|32'hffff_0000); else im32=(im16&32'h0000_ffff); end endmodule

module InstMem(a,op,func,rs,rt,rd,imm,addr); input [31:0] a;

output [5:0] op,func; output [4:0] rs,rt,rd; output [15:0] imm; output [25:0] addr; wire [31:0] do; reg [4:0] rd;

reg [7:0] register [ 1 : 128]; initial begin

assign do[7:0] = ( a == 0 ) ? 0 : register[a]; assign do[15:8] = ( a == 0 ) ? 0 : register[a+1]; assign do[23:16] = ( a == 0 ) ? 0 : register[a+2]; assign do[31:24] = ( a == 0 ) ? 0 : register[a+3]; assign op = do [31:26]; assign func = do [5:0]; assign imm = do [15:0]; assign addr = do [25:0]; assign rs = do [25:21]; assign rt = do [20:16]; always @(op or do) begin case (op)

6'b100011: rd = do [20:16]; default: rd = do [15:11]; endcase end endmodule

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基于MIPS指令的单周期微控制器设计 哈工大

基于MIPS指令的单周期微控制器设计哈工大