专利名称：Method for verifying optimization of
processor link
发明人：Ming-Wei Hsu,Sheng-Chang Peng申请号：US10825239申请日：20040416公开号：US07082385B2公开日：20060725
专利附图：
摘要：A method for verifying optimization of processor link. First, an initial bus widthand an initial bus frequency of a bus coupled between a CPU and a Northbridge are set,such that the bus operates at the initial bus width and the initial bus frequency. Next, a
read request for a Southbridge is generated. Next, a bus disconnection signal is outputby the Southbridge to disconnect the CPU and the Northbridge when the Southbridgereceives the read request. A timer is initialized for calculating an elapsed time value andan optimization verification signal at a first voltage level is generated. Next, a busconnection signal is output by the Southbridge when the elapsed time value reaches apredetermined value. Next, the voltage level of the optimization verification signal istransformed to a second voltage level. Finally, the CPU and the Northbridge arereconnected by the bus according to the bus connection signal, such that the busoperates at another bus operating bus width and another bus operating frequency.
申请人：Ming-Wei Hsu,Sheng-Chang Peng
地址：Taipei TW,Taipei TW
国籍：TW,TW
代理机构：Rabin & Berdo P.C.
更多信息请下载全文后查看
因篇幅问题不能全部显示，请点此查看更多更全内容