SYMBOL PIN I/O
DESCRIPTION
System clock input, either 24MHz or 48MHz. The actual frequency must be specified in register. The default value is 48MHz.
Generated PME event. PCI-clock 33-MHz input. Encoded DMA Request signal. Serialized IRQ input / output.
These signal lines communicate address, control, and data information over the LPC bus between a host and a peripheral.Indicates the start of a new cycle or the termination of a broken cycle.
Reset signal. It can be connected to the PCIRST# signal on the host.
CLKIN 19 INt PME#
86
OD12
PCICLK 21 INtsp3 LDRQ# 22 O12p3 SERIRQ 23 I/O12tp3 LAD[3:0] LFRAME# LRESET#
24-27 29 30
I/O12tp3 INtsp3 INtsp3
Publication Release Date: April 1, 2010
Revision 1.6
W83627UHG/NCT6627UD
SYMBOL PIN DIR#
9
DTRF# STEP#
10
SINF WD#
11
SOUTF WE# DCDF#
13
I/O OD24 O24 OD24 INt OD24 O24 OD24 INt
DESCRIPTION
Direction of the head step motor. An open-drain output. Logic 1 = outward motion Logic 0 = inward motion
UART F Data Terminal Ready. An active low signal informs the modem or data set that the controller is ready to communicate. Step output pulses. This active-low open-drain output produces a pulse to move the head to another track.
Serial Input. This pin is used to receive serial data through the communication link.
Write data. This logic-low open-drain writes pre-compensation serial data to the selected FDD. An open-drain output.
UART F Serial Output. This pin is used to transmit serial data out to the communication link. Write enable. An open-drain output.
Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier.
Track 0. This Schmitt-trigger input from the disk drive is active-low when the head is positioned over the outermost track. This input pin needs to connect a pulled-up 1-KΩ resistor to 5V for Floppy Drive compatibility. General purpose I/O port 6 bit 3.
Write Protected. This active-low Schmitt input from the disk drive indicates that the diskette is write-protected. This input pin needs to connect a pulled-up 1-KΩ resistor to 5V for Floppy Drive compatibility.
General purpose I/O port 6 bit 2.
The read-data input signal from the FDD. This input pin needs to connect a pulled-up 1-KΩ resistor to 5V for Floppy Drive compatibility.
General purpose I/O port 6 bit 1.
Head Select. This open-drain output determines which disk drive head is active. Logic 1 = side 0 Logic 0 = side 1
Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set.
Publication Release Date: April 1, 2010
Revision 1.6
TRAK0#
14
GP63
INtsu
I/OD12ts
WP#
15
GP62
INtsu
I/OD12ts
RDATA#
16
GP61
INtsu I/OD12ts
HEAD#
17
RIF#
OD24
INt
W83627UHG/NCT6627UD
SYMBOL PIN I/O DESCRIPTION
During power on reset, this pin is pulled down internally and is defined as PENKBC, and the power-on values are shown at CR24 bit 2. The PCB layout should reserve space for a 1-kΩ resistor to pull down this pin to ensure the disabling of KBC, and a 1-kΩ resistor is recommended to pull the pin up If wish to enable KBC.
UART B Serial Output. This pin is used to transmit serial data out to the communication link. (This is for W83627UHG only) IR Transmitter output.
General-purpose I/O port 1 bit 2.
UART C Serial Output. This pin is used to transmit serial data out to the communication link. General-purpose I/O port 3 bit 2.
UART D Serial Output. This pin is used to transmit serial data out to the communication link.
Determines PIN 107 and 108 multi-function select. During power-on reset, this pin is pulled down internally and is defined as BEEP function and power LED enable. A 1 kΩ is reserved to pull down and a 1 kΩ resistor is recommended if intending to pull up to enable GPIO output.
General-purpose I/O port 4 bit 2.
UART E Serial Output. This pin is used to transmit serial data out to the communication link. General-purpose I/O port 5 bit 2.
UART F Serial Output. This pin is used to transmit serial data out to the communication link. (This is for W83627UHG only)
Write data. This logic low open drain writes pre-compensation serial data to the selected FDD. An open drain output.
Data Carrier Detect. An active-low signal indicates the modem or data set has detected a data carrier.
Data Carrier Detect. An active-low signal indicates the modem or data set has detected a data carrier. (This is for W83627UHG only)
General-purpose I/O port 1 bit 1.
Data Carrier Detect. An active-low signal indicates the modem or data set has detected a data carrier. General-purpose I/O port 3 bit 1.
Data Carrier Detect. An active-low signal indicates the modem or data set has detected a data carrier.
Publication Release Date: April 1, 2010
Revision 1.6
PENKBC
INcd
SOUTB IRTX GP12 SOUTC GP32 SOUTD
114 83
O8 I/OD8 O8 I/OD8 O8
122
GPI_MUL INcd
GP42 SOUTE GP52 SOUTF
11
WD#
2
I/OD8 O8 I/OD8 O24 OD24
DCDA# 56 INt DCDB# GP11 DCDC# GP31 DCDD#
123 115
INt I/OD12t INt I/OD12t INt
84
W83627UHG/NCT6627UD
SYMBOL PIN I/O GP41 DCDE# GP51 DCDF# WE#
3
I/OD12t INt I/OD12t INt OD24
DESCRIPTION
General-purpose I/O port 4 bit 1.
Data Carrier Detect. An active-low signal indicates the modem or data set has detected a data carrier. General-purpose I/O port 5 bit 1.
Data Carrier Detect. An active-low signal indicates the modem or data set has detected a data carrier. (This is for W83627UHG only)
Write enable. An open drain output.
Ring Indicator. An active-low signal indicates that a ring signal is being received from the modem or data set.
Ring Indicator. An active-low signal indicates that a ring signal is being received from the modem or data set. (This is for W83627UHG only)
General-purpose I/O port 1 bit 0.
Ring Indicator. An active-low signal indicates that a ring signal is being received from the modem or data set. General-purpose I/O port 3 bit 0.
Ring Indicator. An active-low signal indicates that a ring signal is being received from the modem or data set. General-purpose I/O port 4 bit 0.
Ring Indicator. An active-low signal indicates that a ring signal is being received from the modem or data set. General-purpose I/O port 5 bit 0.
Ring Indicator. An active-low signal indicates that a ring signal is being received from the modem or data set. (This is for W83627UHG only)
Head select. This open drain output determines which disk drive head is active. Logic 1 = side 0 Logic 0 = side 1
13
INt RIA# 57 RIB# GP10 RIC# GP30 RID# GP40 RIE# GP50 RIF#
17
HEAD#
OD24
4 124 116
INt I/OD12t INt I/OD12t INt I/OD12t INt I/OD12t INt
85
5.5 KBC Interface
SYMBOL PIN I/O GA20M 58 O12 KBRST# 59 O12
DESCRIPTION
Gate A20 output. This pin is high after system reset. (KBC P21)Keyboard reset. This pin is high after system reset. (KBC P20)
Publication Release Date: April 1, 2010
Revision 1.6
W83627UHG/NCT6627UD
SYMBOL PIN I/O I/OD16ts KCLK 62 Keyboard Clock.
DESCRIPTION
I/OD16ts Keyboard Data. KDAT 63 I/OD16ts PS2 Mouse Clock. MCLK 65 I/OD16ts PS2 Mouse Data. MDAT 66 5.6 Hardware Monitor Interface
SYMBOL PIN I/O BEEP GP21
107
OD12 I/OD12t
DESCRIPTION
Beep function for hardware monitor. This pin is low after system reset.
General-purpose I/O port 2 bit 1.
CASE OPEN Detection. An active-low input from an external device when the case is open. This signal can be latched if pin VBAT is connected to the battery, even if the W83627UHG is turned off.
Pull up a 2-MΩ resistor to VBAT is recommended if useless. Analog Inputs for voltage measurement (Range: 0 to 2.048 V) Analog Inputs for voltage measurement (Range: 0 to 2.048 V).Analog Inputs for voltage measurement (Range: 0 to 2.048 V) Analog Inputs for voltage measurement (Range: 0 to 2.048 V) Reference Voltage (2.048 V)
CASEOPEN# 76 INt
VIN2 VIN1 VIN0 CPUVCORE VREF
98 99 100 101 102
AIN AIN AIN AIN AOUT
Temperature sensor 2 input. It is used for CPU temperature
CPUTIN 103 AIN sensing. Temperature sensor 1 input. It is used for system temperature
SYSTIN 104 AIN sensing. OVT# SMI# CPUFANIN SYSFANIN CPUFANOUT SYSFANOUT
91 93 90 92
I/O12ts O12 OD12 AOUT OD12
Over temperature Shutdown Output. This pin indicates the temperature is over the temperature limit. (Default after LRESET#)
System Management Interrupt channel output. 0 to +5 V amplitude fan tachometer input.
95 OD12
DC/PWM fan output control.
CPUFANOUT and SYSFANOUT are default PWM mode.
PLED 108 Power LED output. This pin is tri-stated as default.
Publication Release Date: April 1, 2010
Revision 1.6
因篇幅问题不能全部显示，请点此查看更多更全内容