KK74HC74A
Dual D Flip-Flop with Set and Reset
The KK74HC74A is identical in pinout to the LS/ALS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.
This device consists of two D flip-flops with individual Set, Reset, and Clock inputs. Information at a D-input is transferred to the corresponding Q output on the next positive going edge of the clock input. Both Q and Q outputs are available from each flip-flop. The Set and Reset inputs are asynchronous.
• Outputs Directly Interface to CMOS, NMOS, and TTL
ORDERING INFORMATION • Operating Voltage Range: 2.0 to 6.0 V
KK74HC74AN Plastic • Low Input Current: 1.0 µA
KK74HC74AD SOIC • High Noise Immunity Characteristic of CMOS Devices
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT FUNCTION TABLE Inputs Outputs Set ResetClockData Q Q L H X X H L
PIN 14 =VCC
PIN 7 = GND
H L X X L H L L X X H*H H H H H*H H L L L H
H H L X No ChangeH H H X No ChangeH H X No Change*Both outputs will remain high as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously. X = don’t care
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KK74HC74A
MAXIMUM RATINGS*
Symbol Parameter VCCVINVOUTIINIOUTICCPDTstg TL
*
Value Unit -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5
±20 ±25 ±50 750 500 -65 to +150
260
V V V mA mA mA mW °C °C
DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin
DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP** SOIC Package**Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. **
Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
VCCVIN, VOUT
TAtr, tf
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1)
VCC =2.0 V VCC =4.5 V VCC =6.0 V
2.0 0 -55 0 0 0
6.0 VCC+125 1000 500 400
V V °C ns
Symbol Parameter Min Max Unit
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
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KK74HC74A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol Parameter Test Conditions VCC
V
Guaranteed Limit 25 °C
to -55°C1.5 3.154.2 0.5 1.351.8 1.9 4.4 5.9 3.985.480.1 0.1 0.1 0.260.26±0.1
≤85 °C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1.0
≤125 °C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±1.0
V Unit
VIH
Minimum High-Level Input Voltage Maximum Low -Level Input Voltage
VOUT=0.1 V or VCC-0.1 V ⎢IOUT⎢≤ 20 µA
VOUT=0.1 V or VCC-0.1 V ⎢IOUT⎢ ≤ 20 µA
2.04.56.02.04.56.02.04.56.0 4.56.02.04.56.0 4.56.06.06.0
VILV
VOH
Minimum High-VIN=VIH or VIL
Level Output Voltage ⎢IOUT⎢ ≤ 20 µA
VIN=VIH or VIL ⎢IOUT⎢ ≤ 4.0 mA ⎢IOUT⎢ ≤ 5.2 mA
V
VOL
Maximum Low-VIN=VIH or VIL
Level Output Voltage ⎢IOUT⎢ ≤ 20 µA
VIN=VIH or VIL ⎢IOUT⎢ ≤ 4.0 mA ⎢IOUT⎢ ≤ 5.2 mA VIN=VCC or GND VIN=VCC or GND IOUT=0µA
V
IINICC
Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package)
µA
2.0 20 80 µA
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KK74HC74A
AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=6.0 ns) Symbol Parameter VCCV Guaranteed Limit 25 °C to -55°C6.0 30 35 100 20 17 105 21 18 75 15 13 10 ≤85°C ≤125°C Unit fmaxMaximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) Maximum Propagation Delay, Clock to Q or Q (Figures 1 and 4) Maximum Propagation Delay, Set or Reset to Q or Q (Figures 2 and 4) Maximum Output Transition Time, Any Output (Figures 1 and 4) Maximum Input Capacitance Power Dissipation Capacitance (Per Flip-Flop) Used to determine the no-load dynamic power consumption:
PD=CPDVCC2f+ICCVCC
2.04.56.02.04.56.02.04.56.02.04.56.0- 4.8 24 28 125 25 21 130 26 22 95 19 16 10 4.0 20 24 150 30 26 160 32 27 110 22 19 10 MHz tPLH, tPHLns tPLH, tPHLns tTLH, tTHLns CIN CPD
pF pF
Typical @25°C,VCC=5.0 V
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TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)
VCCSymbol Parameter V
Guaranteed Limit 25 °C
to-55°C 80 16 14 3.0 3.0 3.0 8.0 8.0 8.0 60 12 10 60 12 10 1000 500 400
≤85°C
≤125°C
Unit
tsuMinimum Setup Time, Data to Clock (Figure 3)
2.04.56.02.04.56.02.04.56.02.04.56.02.04.56.02.04.56.0
100 20 17 3.0 3.0 3.0 8.0 8.0 8.0 75 15 13 75 15 13 1000 500 400
120 24 20 3.0 3.0 3.0 8.0 8.0 8.0 90 18 15 90 18 15 1000 500 400
ns
thMinimum Hold Time, Clock to Data (Figure 3) ns
trec
Minimum Recovery Time, Set or Reset Inactive to Clock (Figure 2)
Minimum Pulse Width, Clock (Figure 1)
ns
twns
twMinimum Pulse Width, Set or Reset (Figure 2) ns
tr, tfMaximum Input Rise and Fall Times (Figure 1) ns
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KK74HC74A
Figure 1. Switching Waveform
Figure 2. Switching Waveform
Figure 3. Switching Waveform Figure 4.Test Circuit
EXPANDED LOGIC DIAGRAM
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KK74HC74A
N SUFFIX PLASTIC DIP(MS - 001AA)A148B17Dimension, mmSymbolABCMIN18.676.1MAX19.697.115.330.361.142.547.620°2.927.620.20.3810°3.818.260.360.561.78FLDFC-T-SEATINGNGD0.25 (0.010) M TKPLANEGHHJMJKLMNNOTES:1. Dimensions “A”, “B” do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side.D SUFFIX SOIC(MS - 012AB)Dimension, mm8A14SymbolAMIN8.553.81.350.330.41.275.270°0.10.195.80.25MAX8.7541.750.511.27HBPBC1G7CR x 45DFG-T-D0.25 (0.010) M TCMKSEATINGPLANEHJFMJKMPR8°0.250.256.20.5NOTES:1. Dimensions A and B do not include mold flash or protrusion.2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B ‑ 0.25 mm (0.010) per side.
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