Ping Pong PHY Interface
The Ping Pong PHY interface is very similar to the PHY only interface except command/address signals are shared by both Channel0 and Channel1 in the Ping Pong PHY. Because command/address signals are shared between Channel0 and Channel1, they are qualified separately by CS_n, CKE, and ODT per channel.
Table4-81 to Table4-84 show the Ping Pong PHY signal interfaces.
Table 4-79:
Ping Pong PHY Command/Address InterfaceSignal
I/O
Description
DRAM ACT_n command signal for four DRAM clock cycles. Bits[1:0] correspond to the first DRAM clock cycle, Bits[3:2] to the second, Bits[5:4] to the third, and Bits[8:7] to the fourth. For center alignment to the DRAM clock with 1N timing, both bits of a given bit pair should be asserted to the same value. See the timing diagrams for examples (PHY Only Interface). All of the command/address ports in this table follow the same eight bits per DRAM pin format. Active-Low. This signal is not used in DDR3 systems.
DRAM address. There are eight bits in the PHY interface for each address bit on the DRAM bus. Bits[7:0] corresponds to DRAM address bit zero on four DRAM clock cycles. Bits[15:8] corresponds to DRAM address bit one on four DRAM clock cycles, and so on. See the timing diagrams for examples (PHY Only Interface). All of the multi-bit DRAM signals in this table follow the same format of one byte of the PHY interface port corresponding to four commands for one DRAM pin. Mixed active-Low and High depending on which type of DRAM
command is being issued, but follows the DRAM pin active-High/Low behavior. The function of each byte of the mc_ADR port depends on whether the memory type is DDR4 or DDR3, and the particular DRAM command that is being issued. These functions match the DRAM address pin functions. For example, with DDR4 memory and the mc_ACT_n port bits asserted High, mc_ADR[135:112] have the function of RAS_n, CAS_n, and WE_n pins.
DDR3 DRAM RAS_n pin. Not used in DDR4 systems.DDR3 DRAM CAS_n pin. Not used in DDR4 systems.DDR3 DRAM WE_n pin. Not used in DDR4 systems.
DRAM bank address. Eight bits for each DRAM bank address.DRAM bank group address. Eight bits for each DRAM pin.
DRAM CKE. Eight bits for each DRAM pin. mc_CKE has a width of CKE_WIDTH × 8 if \"Is CKE to be shared across 2 channels\" option is enabled in Vivado IDE.I
In Ping Pong PHY, bits [CKE_WIDTH × 8/2 – 1:0] is used for Channel0, bits [CKE_WIDTH × 8 – 1:CKE_WIDTH × 8/2] is used for Channel1.In case of dual-rank design, mc_CKE is defines as {Ch1-CKE1, Ch1-CKE0, Ch0-CKE1, Ch0-CKE0}.
mc_ACT_n[7:0]I
mc_ADR
[ADDR_WIDTH × 8 – 1:0]
I
mc_RAS_n[7:0]mc_CAS_n[7:0]mc_WE_n[7:0]mc_BA
[BANK_WIDTH × 8 – 1:0]mc_BG
[BANK_GROUP_WIDTH × 8 – 1:0]
IIIII
mc_CKE
[2 × CKE_WIDTH × 8 – 1:0]
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Chapter 4:Designing with the Core
Table 4-79:
Ping Pong PHY Command/Address Interface (Cont’d)Signal
mc_CS_n
[2 × CS_WIDTH × 8 – 1:0]
I/ODescription
DRAM CS_n. Eight bits for each DRAM pin. Active-Low.
In Ping Pong PHY, bits [CS_WIDTH × 8/2 – 1:0] is used for Channel0, bits [CS_WIDTH × 8 – 1:CS_WIDTH × 8/2] is used for Channel1.In case of dual-rank design, mc_CS_n is defines as {Ch1-CS1, Ch1-CS0, Ch0-CS1, Ch0-CS0}.
DRAM ODT. Eight bits for each DRAM pin. Active-High.
In Ping Pong PHY, bits [ODT_WIDTH × 8/2 – 1:0] is used for Channel0, bits [ODT_WIDTH × 8 – 1:ODT_WIDTH × 8/2] is used for Channel1.In case of dual-rank design, mc_ODT_n is defines as {Ch1-ODT1_n, Ch1-ODT0_n, Ch0-ODT1_n, Ch0-ODT0_n}.
I
mc_ODT
[2 × ODT_WIDTH × 8 – 1:0]
I
mc_C[LR_WIDTH ×8 – 1:0]IDRAM (3DS) Logical rank select address. Eight bits for each DRAM pin.
Table 4-80:Ping Pong PHY Write Data InterfaceSignal
I/O
Description
DRAM write data. There are eight bits for each DQ lane on the DRAM bus. This port transfers data for an entire BL8 write on each system clock cycle. Write data must be provided to the PHY one cycle after the wrDataEn output signal asserts. This protocol must be followed. There is no data buffering in the PHY.
For Ping Pong PHY, wrData[DQ_WIDTH × 8/2 – 1:0] corresponds to channel0, wrData[DQ_WIDTH × 8 – 1:DQ_WIDTH × 8/2] corresponds to channel1.
DRAM write DM/DBI port. There is one bit for each byte of the wrData port, corresponding to one bit for each byte of each burst of a BL8 transfer. wrDataMask is transferred on the same system clock cycle as wrData. Active-High.
wrData
[DQ_WIDTH × 8 – 1:0]
I
wrDataMask
[DM_WIDTH × 8 – 1:0]
I
For DDR3 interface, wrDataMask port appears for Data Mask enabled option in Vivado IDE.
For DDR4 interface, wrDataMask port appears in the \"Data Mask and DBI\" Vivado IDE option values of DM_NO_DBI and DM_DBI_RD.
For Ping Pong PHY, wrDataMask[DM_WIDTH × 8/2 – 1:0] corresponds to channel0, wrDataMask[DM_WIDTH × 8 –1: DM_WIDTH × 8/2] corresponds to channel1.
Write data required. The PHY asserts this port for one cycle for each write CAS command. Your design must provide wrData and wrDataMask at the PHY input ports on the cycle after wrDataEn asserts.
For Ping Pong PHY, Bit[0] corresponds to channel0, Bit[1] corresponds to channel1.
wrDataEn[1:0]O
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Chapter 4:Designing with the Core
Supported Configuration
The following rules outline the configuration supported by the Ping Pong PHY:1.The number of channels supported is two.2.Supports for up to two ranks.
3.Supports for components only which includes twin-die components.4.Memory components supported are x4, x8, and x16.
5.Each channel only has device(s) with the same device width (x4, x8, or x16).
6.Each channel has the same width and the same configuration. Each channel width must
be a multiple of eight.7.The maximum total channel width (DQ_WIDTH) of both channels is 64-bit.
8.Pin allocation is based on the Memory IP rules. Address/control signals map to any bank
which is similar to the Memory IP pin rules. Skip bytes and mix of two channel data bytegroups are allowed.9.Ping Pong PHY design should follow the PCB layout requirement as a regular PHY only
design in total channel width (DQ_WIDTH).10.One MMCM is instantiated in the middle bank.
11.CAS command can be issued to Command Slot0/Slot2 only
Note:The same restriction applies to PHY only designs.
12.Command issued should meet JEDEC timing specification per channel.
13.You have the option to share a CKE pin. In the case when the shared CKE is enabled,
CKE[0] is used for both channels. When CKE sharing is enabled, connect Ch0 CKE toCh1 as well. If you need to use power down mode or self-refresh, the same commandneeds to be issued to both channels.14.Chip select disable is not available for Ping Pong PHY because chip select is used to
distinguish if a given command is sent to Channel0 or Channel1.15.I/O pin planner byte selection view is the same as the regular Memory IP. You must map
Channel-0 to DQ[DQ_WIDTH/2 – 1:0] and Channel-1 to DQ[DQ_WIDTH – 1:DQ_WIDTH/2].Table 4-78:
16324864
Ping Pong PHY Configuration Summary
x4
XXXX
Width/Devicex8
XXXX
x16
–X–X
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