Method of fabricating a wafer level package

专利名称：Method of fabricating a wafer level package发明人：Jong Heon Kim申请号：US10024892申请日：20011218公开号：US06699782B2公开日：20040302

专利附图：

摘要：A fabrication method of wafer level packages capable of improving reliability bymaximizing a contact area of metal wiring and a conductive ball and of simplifyingfabrication processes by reducing the number of sputtering. The disclosed methodcomprises the steps of: providing a substrate having a plurality of chip pads on the upper

part thereof; forming a first insulating layer including a first opening exposing the chippad and a second opening forming a ball land on the substrate; forming metal wiringconnected to the chip pad in a single unit through the first opening and covering thesecond opening to have a ball land on the first insulating layer; forming a second

insulating layer including a third opening which covers the metal wiring, however, exposesthe ball land; and adhering a conductive ball to be in contact with the third opening onthe ball land.

申请人：HYNIX SEMICONDUCTOR INC.

代理机构：Ladas & Parry

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