实验目的
在 MagicSOPC 实验箱上实现8位十进制频率计的设计。被测信号从 CLOCK0（数字信号时钟源）输入，经过检测后测得的频率值用数码管 1~8显示。
实验器材
1、SOPC实验箱
2、计算机（装有Quartus II 7.0软件）
实验预习
1、了解数字频率计设计原理各主要模块的设计方法。 2、提前预习，编写好主模块的VHDL程序。
实验原理
频率即信号1s内振动次数，因此测定信号的频率必须有一个脉宽为1秒的输入信号作为计数允许的信号；1 秒计数结束后，计数值锁入锁存器，并为下一测频计数周期作准备的计数器清零。
数字频率计框图如图18.1所示。由控制、计数、锁存、译码显示四部分组成。工作原理为：控制信号产生电路对系统时钟分频后产生0.5Hz的门控信号gate，锁存允许信号LE,清零信号MR。当gate为高电平时，计数器对被测信号cin进行计数；1s后gate变为低电平，计数器停止计数；当gate为低电平、LE上升沿这两个条件同时满足时，锁存电路将32位计数结果锁存送译码显示电路；当gate为低电平、MR上升沿这两个条件同时满足时，计数器清零，为下一次计数做准备。各信号之间的时序关系见图18.2所示。
系统时钟 显示码（8位） 数码管选通信号（8位） 控制信号产生电路 Gate LE（锁存允许） 选择译码电路 32位 锁存电路 4位 进位 4位 4位 Cin 十进制计数器1 十进制计数器2 MR（清零） 十进制计数器8 图18.1 数字频率计框图
1、控制信号产生电路：根据选定的输入时钟信号设定分频系数，要求输出0.5Hz门控信号gate、1Hz锁存允许信号LE和1Hz清零信号MR。这几个信号控制整个系统的工作，非常关键，要求先锁存后清零，否则计数结果可能丢失，参考时序图18.2所示。 2、计数模块：定义十进制计数器元件，有cp（时钟输入）、MR（清零输入，上升沿有效）、gate（门控信号）三个个输入引脚，Q0~Q3、co（进位）5个输出引脚。功能定义为gate为高电平时在cp上升沿计数；gate为低MR为高时清零。利用元件调用的方法组成8位十进制计数器
3、锁存电路：设计一32位锁存器，定义gate（门控信号）、LE（锁存允许，上升沿有效）d0~d31共34个输入引脚；Q0~Q31共32个输出引脚。功能定义为gate为低时在LE上升沿锁存。
4、译码显示模块：参考数字钟。
1sgate(0.5Hz)CinLE(1Hz)MR(1Hz)计数锁存清零
图18.2 各信号之间的时序关系
程序模块设计
十进制模块 Library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; Entity counter10 IS
PORT(clk,rst:in std_logic; bcd:out std_logic_vector(3 downto 0); up:out std_logic); END entity counter10;
Architecture bhv of counter10 IS
signal bcd_r:std_logic_vector(3 downto 0); signal up_r:std_logic; Begin
Process(clk,rst) Begin
IF rst='1' THEN
bcd_r<=(others=>'0'); up_r<='0';
ELSIF clk'EVENT AND clk='1' THEN
IF bcd_r=\"1001\" THEN
bcd_r<=(others=>'0');up_r<='1'; ELSE bcd_r<=bcd_r+1; up_r<='0'; END IF; END IF;
END PROCESS; bcd<=bcd_r; up<=up_r; END bhv;
信号控制模块 Library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; ENTITY kongzhi IS
PORT(rst_in,sys_clk:in std_logic; gate,lock,rst:out std_logic); END ENTITY;
Architecture one of kongzhi IS
signal count:std_logic_vector(25 downto 0); Begin
PROCESS(sys_clk,rst_in) Begin IF rst_in='0' THEN count<=(others=>'0');gate<='0';lock<='0';rst<='0'; ELSIF sys_clk'EVENT AND sys_clk='1' THEN IF count=\"10110111000110110000000011\"THEN count<=\"00000000000000000000000000\"; gate<='1';lock<='0';rst<='0'; ELSIF count=\"10110111000110110000000010\"THEN gate<='0';lock<='0';rst<='1'; count<=count+1; ELSIF count=\"10110111000110110000000001\"THEN gate<='0';lock<='1';rst<='0'; count<=count+1; ELSIF count=\"10110111000110110000000000\"THEN gate<='0';lock<='0';rst<='0'; count<=count+1; ELSE count<=count+1; gate<='1';lock<='0';rst<='0'; END IF; END IF; END PROCESS;
END one; 锁存模块 Library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; ENTITY suocun IS Port(lock:in std_logic;
data_in:in std_logic_vector(31 downto 0); data_out:out std_logic_vector(31 downto 0)); END entity suocun;
Architecture one of suocun IS
signal data_out_r:std_logic_vector(31 downto 0); Begin
Process(lock) Begin
IF lock='1' THEN
data_out_r<=data_in; END IF;
END PROCESS;
data_out<=data_out_r; END one;
数码管显示译码模块
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_Arith.ALL; USE IEEE.STD_LOGIC_Unsigned.ALL; ENTITY xianshi IS PORT(
clk:IN STD_LOGIC; datain:IN STD_LOGIC_VECTOR(31 DOWNTO 0); dig,seg:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );
END ENTITY;
ARCHITECTURE one OF xianshi IS
SIGNAL counter: std_logic_vector(2 DOWNTO 0); SIGNAL display: std_logic_vector(3 DOWNTO 0); SIGNAL seg_r: std_logic_vector(7 DOWNTO 0); SIGNAL dig_r: std_logic_vector(7 DOWNTO 0);
BEGIN
AAA:PROCESS(clk)
BEGIN
IF clk'EVENT AND clk='1' THEN counter<=counter+1; END IF; END PROCESS AAA;
BBB:PROCESS(counter) BEGIN
CASE counter IS
WHEN \"000\" => dig_r<=\"01111111\"; WHEN \"001\" => dig_r<=\"10111111\"; WHEN \"010\" => dig_r<=\"11011111\"; WHEN \"011\" => dig_r<=\"11101111\"; WHEN \"100\" => dig_r<=\"11110111\"; WHEN \"101\" => dig_r<=\"11111011\"; WHEN \"110\" => dig_r<=\"11111101\"; WHEN \"111\" => dig_r<=\"11111110\"; WHEN OTHERS =>NULL; END CASE; END PROCESS BBB;
CCC:PROCESS(counter,datain) BEGIN
CASE counter IS
WHEN \"000\" => display<=datain(31 DOWNTO 28); WHEN \"001\" => display<=datain(27 DOWNTO 24); WHEN \"010\" => display<=datain(23 DOWNTO 20); WHEN \"011\" => display<=datain(19 DOWNTO 16); WHEN \"100\" => display<=datain(15 DOWNTO 12); WHEN \"101\" => display<=datain(11 DOWNTO 8); WHEN \"110\" => display<=datain(7 DOWNTO 4); WHEN \"111\" => display<=datain(3 DOWNTO 0); WHEN OTHERS =>NULL; END CASE; END PROCESS CCC;
DDD:PROCESS(display) BEGIN CASE display IS WHEN X\"0\"=> seg_r<=X\"c0\"; WHEN X\"1\"=> seg_r<=X\"f9\"; WHEN X\"2\"=> seg_r<=X\"a4\"; WHEN X\"3\"=> seg_r<=X\"b0\"; WHEN X\"4\"=> seg_r<=X\"99\";
WHEN X\"5\"=> seg_r<=X\"92\"; WHEN X\"6\"=> seg_r<=X\"82\"; WHEN X\"7\"=> seg_r<=X\"f8\"; WHEN X\"8\"=> seg_r<=X\"80\"; WHEN X\"9\"=> seg_r<=X\"90\"; WHEN X\"a\"=> seg_r<=X\"88\"; WHEN X\"b\"=> seg_r<=X\"83\"; WHEN X\"c\"=> seg_r<=X\"c6\"; WHEN X\"d\"=> seg_r<=X\"a1\"; WHEN X\"e\"=> seg_r<=X\"86\"; WHEN X\"f\"=> seg_r<=X\"8e\"; WHEN OTHERS =>NULL; END CASE; END PROCESS DDD;
seg<=seg_r; dig<=dig_r;
END ARCHITECTURE;
原理图
clk_1kHzxianshiclk_1kHzdout[31..0]clkdatain[31..0]dig[7..0]seg[7..0]OUTPUTclkINPUTVCCsys_clkOUTPUTdigout[7..0]PIN_A13segout[7..0]inst2instkongzhirst_inINPUTVCCsuocunrst_insys_clkgatelockrstdata[31..0]lockdata_in[31..0]data_out[31..0]PIN_L25dout[31..0]PIN_J8PIN_M3PIN_K6PIN_J6PIN_U10PIN_N9PIN_L10PIN_L9PIN_L6PIN_K5PIN_G3PIN_G4PIN_J3PIN_K4PIN_L3PIN_M4inst32inst3AND2counter10data[3..0]clkbcd[3..0]uprstceshi_inINPUTVCCPIN_N2inst4inst24counter10data[7..4]clkrstbcd[3..0]upinst25counter10data[11..8]clkrstbcd[3..0]upinst26counter10data[15..12]clkrstbcd[3..0]upinst27counter10data[19..16]clkrstbcd[3..0]upinst28counter10data[23..20]clkrstbcd[3..0]upinst29counter10data[27..24]clkrstbcd[3..0]upinst30counter10data[31..28]clkrstbcd[3..0]upinst31
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